MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 343

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IDLE — Idle Bus
27.4.3 J1850 VPW Symbols
Huntsinger’s variable pulse width modulation (VPW) is an encoding technique in which each bit is defined
by the time between successive transitions and by the level of the bus between transitions (for instance,
active or passive). Active and passive bits are used alternately. This encoding technique is used to reduce
the number of bus transitions for a given bit rate.
Each logic 1 or logic 0 contains a single transition and can be at either the active or passive level and one
of two lengths, either 64 μs or 128 μs (t
previous bit. The start-of-frame (SOF), end-of-data (EOD), end-of-frame (EOF), and inter-frame
separation (IFS) symbols always will be encoded at an assigned level and length. See
Each message will begin with an SOF symbol an active symbol and, therefore, each data byte (including
the CRC byte) will begin with a passive bit, regardless of whether it is a logic 1 or a logic 0.
All VPW bit lengths stated in the following descriptions are typical values at a 10.4 kbps bit rate.
Logic 0
Logic 1
Normalization Bit (NB)
Break Signal (BREAK)
Freescale Semiconductor
If the BDLC detects a BREAK symbol while receiving a message, it treats the BREAK as a reception
error and sets the invalid symbol flag in the BSVR, also ignoring the frame it was receiving. If while
receiving a message in 4X mode, the BDLC detects a BREAK symbol, it treats the BREAK as a
reception error, sets the invalid symbol flag, and exits 4X mode (for example, the RX4XE bit in BCR2
is cleared automatically). If bus control is required after the BREAK symbol is received and the IFS
time has elapsed, the programmer must resend the transmission byte using highest priority.
An idle condition exists on the bus during any passive period after expiration of the IFS period (for
instance, ≥ 300 μs). Any node sensing an idle bus condition can begin transmission immediately.
A logic 0 is defined as either:
See
A logic 1 is defined as either:
See
The NB symbol has the same property as a logic 1 or a logic 0. It is only used in IFR message
responses.
The BREAK signal is defined as a passive-to-active transition followed by an active period of at least
240 μs (See
–
–
–
–
Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times
Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times
An active-to-passive transition followed by a passive period 64 μs in length, or
A passive-to-active transition followed by an active period 128 μs in length
An active-to-passive transition followed by a passive period 128 μs in length, or
A passive-to-active transition followed by an active period 64 μs in length
The J1850 protocol BREAK symbol is not related to the HC08 break
module.
Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Chapter 13 Break Module (BRK)
NOM
at 10.4 kbps baud rate), depending upon the encoding of the
NOTE
(a).
(b).
(c)).
BDLC MUX Interface
Figure
27-6.
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