MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 344

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Byte Data Link Controller (BDLC)
Start-of-Frame Symbol (SOF)
End-of-Data Symbol (EOD)
End-of-Frame Symbol (EOF)
Inter-Frame Separation Symbol (IFS)
344
ACTIVE
PASSIVE
ACTIVE
PASSIVE
The SOF symbol is defined as passive-to-active transition followed by an active period 200 μs in length
(See
which follow the SOF symbol to begin with a passive bit, regardless of whether it is a logic 1 or a logic 0.
The EOD symbol is defined as an active-to-passive transition followed by a passive period 200 μs in
length (See
The EOF symbol is defined as an active-to-passive transition followed by a passive period 280 μs in
length (See
transmitted after an EOD symbol is transmitted, after another 80 μs the EOD becomes an EOF,
indicating completion of the message.
The IFS symbol is defined as a passive period 300 μs in length. The 20-μs IFS symbol contains no
transition, since when used it always appends to an EOF symbol (See
Symbols with Nominal Symbol Times
Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times
Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times
Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times
ACTIVE
PASSIVE
ACTIVE
PASSIVE
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Figure 27-6. J1850 VPW Symbols with Nominal Symbol Times
(F) END OF FRAME
(C) BREAK
≥ 240 μs
280 μs
(G) INTER-FRAME
(g)).
SEPARATION
128 μs
128 μs
20 μs
300 μs
(A) LOGIC 0
(B) LOGIC 1
(D) START OF FRAME
200 μs
OR
OR
IDLE > 300 μs
(H) IDLE
(d)). This allows the data bytes
Figure 27-6. J1850 VPW
(e)).
(f)). If no IFR byte is
64 μs
64 μs
Freescale Semiconductor
(E) END OF DATA
200 μs