MC908AZ60ACFU Freescale Semiconductor, MC908AZ60ACFU Datasheet - Page 398

• Manufacturer Part Number: MC908AZ60ACFU
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MC68HC908AZ60E
B.7 Configuration Register (CONFIG-3)
This section describes the configuration register (CONFIG-3). This register is unused on the
MC68HC908AZ60A. This register contains one bit that configures the following option:
The configuration register is a write-once register. Once the register is written, further writes will have no
effect until a reset occurs.
SPISRD — SPI Slew Rate Disable
B.8 SCI
The incorrect operation, signified by the "Note" in the Idle Characters paragraph of the SCI section of this
document has been corrected. The following note does not apply to the MC68HC908AZ60E.
B.9 MSCAN
The MSCAN08 errata on the MC68HC908AZ60A has been fixed on the MC68HC908AZ60E. For 32-bit
and 16-bit identifier acceptance modes, an extended ID CAN frame with a stuff bit between ID16 and ID15
will not be rejected. No software work around is required.
398
Disables slew rate control for the SPI pins
This bit disables the slew rate controlled outputs for SCK, MOSI, and MISO pins.
1 = SPI slew rate is disabled
0 = SPI slew rate is enabled
Address: $FE0B
When a break sequence is followed immediately by an idle character, this
SCI design exhibits a condition in which the break character length is
reduced by one half bit time. In this instance, the break sequence will
consist of a valid start bit, eight or nine data bits (as defined by the M bit in
SCC1) of logic 0 and one half data bit length of logic 0 in the stop bit position
followed immediately by the idle character. To ensure a break character of
the proper length is transmitted, always queue up a byte of data to be
transmitted while the final break sequence is in progress.
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Bit 7
R
R
0
Figure B-4. Configuration Register (CONFIG-3)
= Reserved
R
6
0
R
5
0
NOTE
R
4
0
R
3
0
R
2
0
SPISRD
1
0
Freescale Semiconductor
Bit 0
R
0