MCF5307CFT66B Freescale Semiconductor, MCF5307CFT66B Datasheet
MCF5307CFT66B
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... Freescale Semiconductor, Inc. MCF5307 ColdFire Integrated Microprocessor For More Information On This Product, Go to: www.freescale.com User’s Manual MCF5307UM/D Rev. 2.0, 08/2000 ® ...
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... Freescale Semiconductor, Inc. ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc registered trademark of Philips Semiconductors Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...
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... Freescale Semiconductor, Inc. Part I: MCF5307 Processor Core Hardware Multiply/Accumulate (MAC) Unit Part II: System Integration Module (SIM) Synchronous/Asynchronous DRAM Controller Module Parallel Port (General-Purpose I/O) IEEE 1149.1 Test Access Port (JTAG) Glossary of Terms and Abbreviations For More Information On This Product, Overview ColdFire Core ...
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... Freescale Semiconductor, Inc. Overview 1 Part I: MCF5307 Processor Core Part I ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 Part II: System Integration Module (SIM) Part II SIM Overview 6 Phase-Locked Loop (PLL Module 9 Interrupt Controller 10 Chip-Select Module 11 Synchronous/Asynchronous DRAM Controller Module Part III ...
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... Freescale Semiconductor, Inc. Paragraph Number 1.1 Features ............................................................................................................... 1-1 1.2 MCF5307 Features.............................................................................................. 1-4 1.2.1 Process ............................................................................................................ 1-6 1.3 ColdFire Module Description ............................................................................. 1-7 1.3.1 ColdFire Core ................................................................................................. 1-7 1.3.1.1 Instruction Fetch Pipeline (IFP).................................................................. 1-7 1.3.1.2 Operand Execution Pipeline (OEP) ............................................................ 1-7 1.3.1.3 MAC Module.............................................................................................. 1-7 1.3.1.4 Integer Divide Module ...
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... Freescale Semiconductor, Inc. Paragraph Number 2.1 Features and Enhancements.............................................................................. 2-21 2.1.1 Clock-Multiplied Microprocessor Core........................................................ 2-22 2.1.2 Enhanced Pipelines ....................................................................................... 2-22 2.1.2.1 Instruction Fetch Pipeline (IFP)................................................................ 2-23 2.1.2.1.1 Branch Acceleration ............................................................................. 2-23 2.1.2.2 Operand Execution Pipeline (OEP) .......................................................... 2-24 2.1.2.2.1 Illegal Opcode Handling....................................................................... 2-24 2.1.2.2.2 Hardware Multiply/Accumulate (MAC) Unit ...
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... Freescale Semiconductor, Inc. Paragraph Number 2.7.5 Branch Instruction Execution Times ............................................................ 2-46 2.8 Exception Processing Overview ....................................................................... 2-47 2.8.1 Exception Stack Frame Definition................................................................ 2-49 2.8.2 Processor Exceptions .................................................................................... 2-50 Hardware Multiply/Accumulate (MAC) Unit 3.1 Overview............................................................................................................. 3-1 3.1.1 MAC Programming Model............................................................................. 3-2 3.1.2 General Operation........................................................................................... 3-3 3 ...
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... Freescale Semiconductor, Inc. Paragraph Number 4.9.5 Memory Accesses for Cache Maintenance................................................... 4-17 4.9.5.1 Cache Filling............................................................................................. 4-17 4.9.5.2 Cache Pushes ............................................................................................ 4-18 4.9.5.2.1 Push and Store Buffers ......................................................................... 4-18 4.9.5.2.2 Push and Store Buffer Bus Operation................................................... 4-18 4.9.6 Cache Locking .............................................................................................. 4-19 4.10 Cache Registers................................................................................................. 4-21 4 ...
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... Freescale Semiconductor, Inc. Paragraph Number 5.5.3.3.4 Write Memory Location ( 5.5.3.3.5 Dump Memory Block ( 5.5.3.3.6 Fill Memory Block ( 5.5.3.3.7 Resume Execution ( 5.5.3.3.8 No Operation ( 5.5.3.3.9 Synchronize PC to the PST/DDATA Lines ( 5.5.3.3.10 Read Control Register ( 5.5.3.3.11 Write Control Register ( 5.5.3.3.12 Read Debug Module Register ( 5 ...
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... Freescale Semiconductor, Inc. Paragraph Number Phase-Locked Loop (PLL) 7.1 Overview............................................................................................................. 7-1 7.1.1 PLL:PCLK Ratios........................................................................................... 7-2 7.2 PLL Operation .................................................................................................... 7-2 7.2.1 Reset/Initialization .......................................................................................... 7-2 7.2.2 Normal Mode.................................................................................................. 7-2 7.2.3 Reduced-Power Mode..................................................................................... 7-2 7.2.4 PLL Control Register (PLLCR)...................................................................... 7-3 7.3 PLL Port List ...................................................................................................... 7-3 7 ...
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... Freescale Semiconductor, Inc. Paragraph Number 9.1 Overview............................................................................................................. 9-1 9.2 Interrupt Controller Registers ............................................................................. 9-2 9.2.1 Interrupt Control Registers (ICR0–ICR9) ...................................................... 9-3 9.2.2 Autovector Register (AVR) ............................................................................ 9-5 9.2.3 Interrupt Pending and Mask Registers (IPR and IMR)................................... 9-6 9.2.4 Interrupt Port Assignment Register (IRQPAR) .............................................. 9-7 10 ...
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... Freescale Semiconductor, Inc. Paragraph Number 11.3.3.2 Burst Page-Mode Operation ................................................................... 11-12 11.3.3.3 Continuous Page Mode........................................................................... 11-13 11.3.3.4 Extended Data Out (EDO) Operation..................................................... 11-15 11.3.3.5 Refresh Operation ................................................................................... 11-16 11.4 Synchronous Operation................................................................................... 11-16 11.4.1 DRAM Controller Signals in Synchronous Mode...................................... 11-17 11.4.2 Using Edge Select (EDGESEL) ................................................................. 11-18 11 ...
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... Freescale Semiconductor, Inc. Paragraph Number 12.4.3 Byte Count Registers (BCR0–BCR3)........................................................... 12-7 12.4.4 DMA Control Registers (DCR0–DCR3)...................................................... 12-8 12.4.5 DMA Status Registers (DSR0–DSR3) ....................................................... 12-10 12.4.6 DMA Interrupt Vector Registers (DIVR0–DIVR3) ................................... 12-11 12.5 DMA Controller Module Functional Description........................................... 12-11 12 ...
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... Freescale Semiconductor, Inc. Paragraph Number 14.3.4 UART Clock-Select Registers (UCSRn)...................................................... 14-8 14.3.5 UART Command Registers (UCRn) ............................................................ 14-9 14.3.6 UART Receiver Buffers (URBn) ............................................................... 14-11 14.3.7 UART Transmitter Buffers (UTBn) ........................................................... 14-11 14.3.8 UART Input Port Change Registers (UIPCRn).......................................... 14-12 14.3.9 UART Auxiliary Control Register (UACRn)............................................. 14-12 14 ...
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... Freescale Semiconductor, Inc. Paragraph Number 16.1 Package ............................................................................................................. 16-1 16.2 Pinout ................................................................................................................ 16-1 16.3 Mechanical Diagram......................................................................................... 16-8 16.4 Case Drawing.................................................................................................... 16-9 17.1 Overview........................................................................................................... 17-1 17.2 MCF5307 Bus Signals ...................................................................................... 17-7 17.2.1 Address Bus .................................................................................................. 17-7 17.2.1.1 Address Bus (A[23:0]).............................................................................. 17-7 17.2.1.2 Address Bus (A[31:24]/PP[15:8]) ............................................................ 17-7 17 ...
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... Freescale Semiconductor, Inc. Paragraph Number 17.5.5.3 D[6:5]—Port Size Configuration (PS_CONFIG[1:0]) ........................... 17-14 17.5.6 D4—Address Configuration (ADDR_CONFIG) ....................................... 17-14 17.5.7 D[3:2]—Frequency Control PLL (FREQ[1:0] ..........................................) 17-15 17.5.8 D[1:0]—Divide Control PCLK to BCLKO (DIVIDE[1:0])....................... 17-15 17.6 Chip-Select Module Signals ........................................................................... 17-15 17.6.1 Chip-Select (CS[7:0]) ................................................................................. 17-16 17 ...
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... Freescale Semiconductor, Inc. Paragraph Number 18.1 Features ............................................................................................................. 18-1 18.2 Bus and Control Signals ................................................................................... 18-1 18.3 Bus Characteristics............................................................................................ 18-2 18.4 Data Transfer Operation ................................................................................... 18-3 18.4.1 Bus Cycle Execution..................................................................................... 18-4 18.4.2 Data Transfer Cycle States ........................................................................... 18-5 18.4.3 Read Cycle.................................................................................................... 18-7 18.4.4 Write Cycle ................................................................................................... 18-8 18 ...
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... Freescale Semiconductor, Inc. Paragraph Number 19.4.4 JTAG Bypass Register................................................................................ 19-10 19.5 Restrictions ..................................................................................................... 19-10 19.6 Disabling IEEE Standard 1149.1 Operation ................................................... 19-11 19.7 Obtaining the IEEE Standard 1149.1.............................................................. 19-12 20.1 General Parameters ........................................................................................... 20-1 20.2 Clock Timing Specifications............................................................................. 20-2 20.3 Input/Output AC Timing Specifications........................................................... 20-3 20 ...
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... Freescale Semiconductor, Inc. Figure Number 1-1 MCF5307 Block Diagram............................................................................................. 1-2 1-2 UART Module Block Diagram..................................................................................... 1-9 1-3 PLL Module ................................................................................................................ 1-12 1-4 ColdFire MCF5307 Programming Model .................................................................. 1-13 2-1 ColdFire Enhanced Pipeline ....................................................................................... 2-23 2-2 ColdFire Multiply-Accumulate Functionality Diagram ............................................. 2-25 2-3 ColdFire Programming Model.................................................................................... 2-27 2-5 Status Register (SR) ...
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... Freescale Semiconductor, Inc. Figure Number 5-10 Program Counter Breakpoint Register (PBR)............................................................. 5-14 5-11 Program Counter Breakpoint Mask Register (PBMR) ............................................... 5-14 5-12 Trigger Definition Register (TDR) ............................................................................. 5-15 5-13 BDM Serial Interface Timing ..................................................................................... 5-18 5-14 Receive BDM Packet.................................................................................................. 5-19 5-15 Transmit BDM Packet ................................................................................................ 5-19 5-16 BDM Command Format ...
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... Freescale Semiconductor, Inc. Figure Number 6-9 Default Bus Master Register (MPARK) ..................................................................... 6-11 6-10 Round Robin Arbitration (PARK = 00)...................................................................... 6-12 6-11 Park on Master Core Priority (PARK = 01) ............................................................... 6-13 6-12 Park on DMA Module Priority (PARK = 10)............................................................. 6-13 6-13 Park on Current Master Priority (PARK = 01) ........................................................... 6-14 7-1 PLL Module Block Diagram ........................................................................................ 7-1 7-2 PLL Control Register (PLLCR) ...
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... Freescale Semiconductor, Inc. Figure Number 11-15 DRAM Control Register (DCR) (Synchronous Mode) ............................................ 11-19 11-16 DACR0 and DACR1 Registers (Synchronous Mode).............................................. 11-20 11-17 DRAM Controller Mask Registers (DMR0 and DMR1).......................................... 11-22 11-18 Burst Read SDRAM Access ..................................................................................... 11-28 11-19 Burst Write SDRAM Access .................................................................................... 11-29 11-20 Synchronous, Continuous Page-Mode Access— ...
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... Freescale Semiconductor, Inc. Figure Number 14-10 UART Auxiliary Control Register (UACRn) ........................................................... 14-13 14-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)........................................ 14-13 14-12 UART Divider Upper Register (UDUn)................................................................... 14-14 14-13 UART Divider Lower Register (UDLn)................................................................... 14-14 14-14 UART Interrupt Vector Register (UIVRn) ............................................................... 14-15 14-15 UART Input Port Register (UIPn) ...
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... Freescale Semiconductor, Inc. Figure Number 18-19 Longword Read from an 8-Bit Port, External Termination...................................... 18-16 18-20 Longword Read from an 8-Bit Port, Internal Termination ....................................... 18-16 18-21 Example of a Misaligned Longword Transfer (32-Bit Port) .................................... 18-17 18-22 Example of a Misaligned Word Transfer (32-Bit Port) ............................................ 18-17 18-23 Interrupt-Acknowledge Cycle Flowchart ...
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... Freescale Semiconductor, Inc. Table Number 1-1 User-Level Registers................................................................................................... 1-14 1-2 Supervisor-Level Registers......................................................................................... 1-14 2-1 CCR Field Descriptions ............................................................................................. 2-28 2-2 MOVEC Register Map ............................................................................................... 2-29 2-3 Status Field Descriptions ............................................................................................ 2-30 2-4 Integer Data Formats................................................................................................... 2-31 2-5 ColdFire Effective Addressing Modes........................................................................ 2-34 2-6 Notational Conventions .............................................................................................. 2-34 2-7 User-Mode Instruction Set Summary ...
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... Freescale Semiconductor, Inc. Table Number 5-2 Processor Status Encoding............................................................................................ 5-4 5-3 BDM/Breakpoint Registers........................................................................................... 5-7 5-4 AATR Field Descriptions ............................................................................................. 5-8 5-5 ABLR Field Description ............................................................................................... 5-9 5-6 ABHR Field Description............................................................................................... 5-9 5-7 BAAR Field Descriptions ........................................................................................... 5-10 5-8 CSR Field Descriptions .............................................................................................. 5-11 5-9 DBR Field Descriptions.............................................................................................. 5-13 5-10 DBMR Field Descriptions ...
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... Freescale Semiconductor, Inc. Table Number 9-8 IRQPAR Field Descriptions ......................................................................................... 9-8 10-1 Chip-Select Module Signals ....................................................................................... 10-1 10-2 Byte Enables/Byte Write Enable Signal Settings ....................................................... 10-2 10-3 Accesses by Matches in CSCRs and DACRs ............................................................. 10-3 10-4 D7/AA, Automatic Acknowledge of Boot CS0.......................................................... 10-4 10-5 D[6:5]/PS[1:0], Port Size of Boot CS0 ....................................................................... 10-4 10-6 Chip-Select Registers ...
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... Freescale Semiconductor, Inc. Table Number 11-34 DCR Initialization Values......................................................................................... 11-35 11-35 DACR Initialization Values...................................................................................... 11-36 11-36 DMR0 Initialization Values...................................................................................... 11-37 11-37 Mode Register Initialization ..................................................................................... 11-38 12-1 DMA Signals .............................................................................................................. 12-2 12-2 Memory Map for DMA Controller Module Registers................................................ 12-5 12-3 DCRn Field Descriptions............................................................................................ 12-8 12-4 DSRn Field Descriptions ...
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... Freescale Semiconductor, Inc. Table Number 17-10 Data Pin Configuration ............................................................................................. 17-12 17-11 D7 Selection of CS0 Automatic Acknowledge ........................................................ 17-13 17-12 D6 and D5 Selection of CS0 Port Size ..................................................................... 17-13 17-13 D4/ADDR_CONFIG, Address Pin Assignment....................................................... 17-13 17-14 CLKIN Frequency .................................................................................................... 17-13 17-15 BCLKO/PSTCLK Divide Ratios.............................................................................. 17-14 17-16 Processor Status Signal Encodings ........................................................................... 17-19 18-1 ColdFire Bus Signal Summary ...
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... Freescale Semiconductor, Inc. Table Number A-6 UART0 Control Registers............................................................................................ A-4 A-7 UART1 Control Registers............................................................................................ A-6 A-8 Parallel Port Memory Map........................................................................................... A Interface Memory Map.......................................................................................... A-8 A-10 DMA Controller Registers........................................................................................... A-8 xxx For More Information On This Product, TABLES Title MCF5307 User’s Manual Go to: www ...
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... Freescale Semiconductor, Inc. About This Book The primary objective of this user’s manual is to define the functionality of the MCF5307 processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in the disclaimers on the title page of this book. As with any technical documentation the readers’ ...
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... Freescale Semiconductor, Inc. Organization — Chapter 4, “Local Memory.” This chapter describes the MCF5307 implementation of the ColdFire V3 local memory specification. It consists of the two following major sections. – Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization ...
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... Freescale Semiconductor, Inc. • Part III, “Peripheral Module,” describes the operation and configuration of the MCF5307 DMA, timer, UART, and parallel port modules, and describes how they interface with the system integration unit, described in Part II. — Chapter 12, “DMA Controller Module,” provides an overview of the DMA controller module and describes in detail its signals and registers ...
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... Freescale Semiconductor, Inc. Suggested Reading This manual includes the following appendix: • Appendix A, “List of Memory Maps,” lists the entire address-map for MCF5307 memory-mapped registers. This manual also includes a glossary and an index. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the ColdFire architecture ...
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... Freescale Semiconductor, Inc. italics Italics indicate variable command parameters. Book titles in text are set in italics. 0x0 Prefix to denote hexadecimal number 0b0 Prefix to denote binary number REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For example, RAMBAR[BA] identifi ...
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... Freescale Semiconductor, Inc. Acronyms and Abbreviations Table i. Acronyms and Abbreviated Terms (Continued) Term GPIO General-purpose I Inter-integrated circuit IEEE Institute for Electrical and Electronics Engineers IFP Instruction fetch pipeline IPL Interrupt priority level JEDEC Joint Electron Device Engineering Council JTAG Joint Test Action Group LIFO Last-in, fi ...
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... Freescale Semiconductor, Inc. Terminology and Notational Conventions Table ii shows notational conventions used throughout this document. Table ii Notational Conventions Instruction cc Logical condition (example: NE for not equal) An Any address register n (example address register 3) Ay,Ax Source and destination address registers, respectively Dn Any data register n (example data register 5) ...
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... Freescale Semiconductor, Inc. Terminology and Notational Conventions Table ii Notational Conventions (Continued) Instruction ic Instruction cache # <vector> Identifies the 4-bit vector number for trap instructions identifies an indirect data address referencing memory <xxx> identifies an absolute address referencing memory dn Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) SF Scale factor (x1, x2, x4 for indexed addressing mode, < ...
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... Freescale Semiconductor, Inc. Table ii Notational Conventions (Continued) Instruction Condition Code Register Bit Names C Carry N Negative V Overflow X Extend Z Zero For More Information On This Product, Terminology and Notational Conventions Operand Syntax About This Book Go to: www.freescale.com xxxix ...
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... Freescale Semiconductor, Inc. Terminology and Notational Conventions xl For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 1 Overview This chapter is an overview of the MCF5307 ColdFire processor. It includes general descriptions of the modules and features incorporated in the MCF5307. 1.1 Features The MCF5307 integrated microprocessor combines a V3 ColdFire processor core with the following components, as shown in Figure 1-1: • ...
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... Freescale Semiconductor, Inc. Features JTAG Debug Module PSTCLK BCLKO (sent off-chip and to on-chip peripherals) CLKIN PCLK PLL X n RSTI RSTO Local Memory Bus SYSTEM INTEGRATION MODULE (SIM) PLL Control System Control PLL RSR SWIVR SYPCR SWSR DRAM Controller Chip-Select Module DRAM Control ...
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... Freescale Semiconductor, Inc. Features common to many embedded applications, such as DMAs, various DRAM controller interfaces, and on-chip memories, are integrated using advanced process technologies. The MCF5307 extends the legacy of Motorola’s 68K family by providing a compatible path for 68K and ColdFire customers in which development tools and customer code can be leveraged ...
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... Freescale Semiconductor, Inc. MCF5307 Features 1.2 MCF5307 Features The following list summarizes MCF5307 features: • ColdFire processor core — Variable-length RISC, clock-multiplied Version 3 microprocessor core — Fully code compatible with Version 2 processors — Two independent decoupled pipelines: four-stage instruction fetch pipeline (IFP) and two-stage operand execution pipeline (OEP) — ...
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... Freescale Semiconductor, Inc. • DMA controller — Four fully programmable channels: two support external requests — Dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability — Source/destination address pointers that can increment or remain constant — 24-bit transfer counter per channel — ...
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... Freescale Semiconductor, Inc. MCF5307 Features FLASH, and memory-mapped I/O devices — Eight fully programmable chip selects, each with a base address register — Programmable wait states and port sizes per chip select — User-programmable processor clock/input clock frequency ratio — Programmable interrupt controller — ...
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... Freescale Semiconductor, Inc. 1.3 ColdFire Module Description The following sections provide overviews of the various modules incorporated in the MCF5307. 1.3.1 ColdFire Core The Version 4 ColdFire core consists of two independent and decoupled pipelines to maximize performance—the instruction fetch pipeline (IFP) and the operand execution pipeline (OEP) ...
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... Freescale Semiconductor, Inc. ColdFire Module Description 1.3.1.5 8-Kbyte Unified Cache The MCF5307 architecture includes an 8-Kbyte unified cache. This four-way, set-associative cache provides pipelined, single-cycle access on cached instructions and operands. As with all ColdFire caches, the cache controller implements a non-lockup, streaming design ...
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... Freescale Semiconductor, Inc. System Integration Module (SIM) Interrupt Controller Figure 1-2. UART Module Block Diagram Each UART module consists of the following major functional areas: • Serial communication channel • 16-bit divider for clock generation • Internal channel control logic • Interrupt control logic Each UART contains an programmable clock-rate generator ...
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... Freescale Semiconductor, Inc. ColdFire Module Description short distances among several devices. The I multiple-master modes. 1.3.7 System Interface The MCF5307 processor provides a direct interface to 8-, 16-, and 32-bit FLASH, SRAM, ROM, and peripheral devices through the use of fully programmable chip selects and write enables ...
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... Freescale Semiconductor, Inc. 1.3.7.5 JTAG To help with system diagnostics and manufacturing testing, the MCF5307 processor includes dedicated user-accessible test logic that complies with the IEEE 1149.1a standard for boundary-scan testability, often referred to as the Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1a standard. ...
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... Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set CLKIN CLKIN X 4 FREQ[1:0] RSTI DIVIDE[1:0] The PLL module’s three modes of operation are described as follows. • Reset mode—When RSTI is asserted, the PLL enters reset mode. At reset, the PLL asserts RSTO from the MCF5307. The core:bus frequency ratio and other MCF5307 confi ...
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... Freescale Semiconductor, Inc. control. The supervisor programming model provides access to the same registers as the user model, plus additional registers for configuring on-chip system resources, as described in Section 1.4.3, “Supervisor Registers.” Exceptions (including interrupts) are handled in supervisor mode. 1.4.1 Programming Model Figure 1-4 shows the MCF5307 programming model ...
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... Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set 1.4.2 User Registers The user programming model is shown in Figure 1-4 and summarized in Table 1-1. Table 1-1. User-Level Registers Register Data registers These 32-bit registers are for bit, byte, word, and longword operands. They can also be used as (D0– ...
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... Freescale Semiconductor, Inc. 1.4.4 Instruction Set The ColdFire instruction set supports high-level languages and is optimized for those instructions most commonly generated by compilers in embedded applications. Table 2-8 provides an alphabetized listing of the ColdFire instruction set opcodes, supported operation sizes, and assembler syntax. For two-operand instructions, the first operand is generally the source operand and the second is the destination ...
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... Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set 1-16 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Intended Audience Part I is intended for system designers who need a general understanding of the functionality supported by the MCF5307. It also describes the operation of the MCF5307 Contents • Chapter 2, “ColdFire Core,” provides an overview of the microprocessor core of the MCF5307. The chapter begins with a description of enhancements from the V2 ColdFire core, and then fully describes the V3 programming model implemented on the MCF5307 ...
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... Freescale Semiconductor, Inc. Suggested Reading The following literature may be helpful with respect to the topics in Part I: • ColdFire Programmers Reference Manual, R1.0 (MCF5200PRM/AD) • Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield Acronyms and Abbreviations Table I-i contains acronyms and abbreviations are used in Part I. ...
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... Freescale Semiconductor, Inc. Table I-i. Acronyms and Abbreviated Terms (Continued) Term MAC Multiple accumulate unit MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter PCLK Processor clock ...
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... Freescale Semiconductor, Inc. I-xx For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 2 ColdFire Core This chapter provides an overview of the microprocessor core of the MCF5307. The chapter begins with a description of enhancements from the Version 2 (V2) ColdFire core, and then fully describes the V3 programming model implemented on the MCF5307. It also includes a full description of exception handling, data formats, an instruction set summary, and a table of instruction timings ...
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... Freescale Semiconductor, Inc. Features and Enhancements 2.1.1 Clock-Multiplied Microprocessor Core The MCF5307 incorporates a clock-multiplying phase-locked loop (PLL). Increasing the internal speed of the core also allows higher performance while providing the system designer with an easy-to-use lower speed system interface. The frequency of the processor complex can be 2x, 3x the external bus speed. ...
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... Freescale Semiconductor, Inc. IAG IC1 Instruction Fetch IC2 Pipeline IED IB Instruction Buffer Decode & Select, DSOC Operand Fetch Operand Execution Pipeline AGEX Figure 2-1. ColdFire Enhanced Pipeline 2.1.2.1 Instruction Fetch Pipeline (IFP) Because the fetch and execution pipelines are decoupled by an eight-instruction FIFO buffer, the IFP can prefetch instructions before the OEP needs them, minimizing stalls ...
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... Freescale Semiconductor, Inc. Features and Enhancements For example unconditional BRA instruction is detected, the IED calculates the target of the BRA instruction, and the IAG immediately begins fetching at the target address. Because of the decoupled nature of the two pipelines, the target instruction is available to the OEP immediately after the BRA instruction, giving it a single-cycle execution time. ...
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... Freescale Semiconductor, Inc. Figure 2-2 shows basic functionality of the MAC. A full set of instructions are provided for signed and unsigned integers plus signed, fixed-point fractional input operands. Figure 2-2. ColdFire Multiply-Accumulate Functionality Diagram The MAC provides functionality in the following three related areas, which are described in detail in Chapter 3, “ ...
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... Freescale Semiconductor, Inc. Programming Model On-chip breakpoint resources include the following: • Configuration/status register (CSR) • Background debug mode (BDM) address attributes register (BAAR) • Bus attributes and mask register (AATR) • Breakpoint registers. These can be used to define triggers combining address, data, and PC conditions in single- or dual-level defi ...
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... Freescale Semiconductor, Inc Figure 2-3. ColdFire Programming Model 2.2.1 User Programming Model As Figure 2-3 shows, the user programming model consists of the following registers: • 16 general-purpose 32-bit registers, D0–D7 and A0–A7 • 32-bit program counter • 8-bit condition code register 2.2.1.1 Data Registers (D0–D7) Registers D0– ...
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... Freescale Semiconductor, Inc. Programming Model 2.2.1.3 Stack Pointer (A7, SP) The processor core supports a single hardware stack pointer (A7) used during stacking for subroutine calls, returns, and exception handling. The stack pointer is implicitly referenced by certain operations and can be explicitly referenced by any instruction specifying an address register ...
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... Freescale Semiconductor, Inc. Table 2-1. CCR Field Descriptions (Continued) Bits Name 1 V Overflow condition code bit. Set if an arithmetic overflow occurs, implying that the result cannot be represented in the operand size; otherwise cleared Carry condition code bit. Set if a carry-out of the data operand msb occurs for an addition borrow occurs in a subtraction ...
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... Freescale Semiconductor, Inc. Programming Model System byte Field T — — Reset R/W R/W R R/W R/W R Figure 2-5. Status Register (SR) Table 2-3 describes SR fields. Table 2-3. Status Field Descriptions Bits Name 15 T Trace enable. When T is set, the processor performs a trace exception after every instruction. ...
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... Freescale Semiconductor, Inc. 2.2.2.4 Access Control Registers (ACR0–ACR1) The access control registers (ACR0–ACR1) define attributes for two user-defined memory regions. Attributes include definition of cache mode, write protect and buffer write enables. See Section 4.10.2, “Access Control Registers (ACR0–ACR1).” ...
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... Freescale Semiconductor, Inc. Organization of Data in Registers high-order portion does not change. The least significant bit (lsb) of all integer sizes is zero, the most-significant bit (msb longword integer is 31, the msb of a word integer is 15, and the msb of a byte integer is 7. ...
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... Freescale Semiconductor, Inc. organization is shown in Figure 2- Word 0x0000_0000 Byte 0x0000_0000 Byte 0x0000_0001 Word 0x0000_0004 Byte 0x0000_0004 Byte 0x0000_0005 Word 0xFFFF_FFFC Byte 0xFFFF_FFFC Byte 0xFFFF_FFFD Figure 2-9. Memory Operand Addressing 2.5 Addressing Mode Summary Addressing modes are categorized by how they are used. Data addressing modes refer to data operands ...
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... Freescale Semiconductor, Inc. Instruction Set Summary Table 2-5. ColdFire Effective Addressing Modes Addressing Modes Syntax Register direct Data Dn Address An Register indirect Address (An) Address with (An)+ Postincrement –(An) Address with (d , An) 16 Predecrement Address with Displacement Address register indirect with index (d , An, 8 8-bit displacement ...
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... Freescale Semiconductor, Inc. Table 2-6. Notational Conventions (Continued) Instruction An Any address register n (example address register 3) Ay,Ax Source and destination address registers, respectively Dn Any data register n (example data register 5) Dy,Dx Source and destination data registers, respectively Rc Any control register (example VBR is the vector base register) ...
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... Freescale Semiconductor, Inc. Instruction Set Summary Table 2-6. Notational Conventions (Continued) Instruction + Arithmetic addition or postincrement indicator – Arithmetic subtraction or predecrement indicator x Arithmetic multiplication / Arithmetic division ~ Invert; operand is logically complemented & Logical AND | Logical OR ^ Logical exclusive OR << Shift left (example: D0 << shift D0 left 3 bits) > ...
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... Freescale Semiconductor, Inc. Table 2-6. Notational Conventions (Continued) Instruction P Branch prediction C Carry N Negative V Overflow X Extend Z Zero 2.6.1 Instruction Set Summary Table 2-7 lists implemented user-mode instructions by opcode. Table 2-7. User-Mode Instruction Set Summary Instruction Operand Syntax ADD Dy,<ea>x .L <ea>y,Dx .L ADDA < ...
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... Freescale Semiconductor, Inc. Instruction Set Summary Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax CMPI <ea>y,Dx .L DIVS <ea-1>y,Dx .W <ea>y,Dx .L DIVU <ea-1>y,Dx .W Dy,<ea>x .L EOR Dy,<ea>x .L EORI #<data>,Dx .L EXT #<data>,Dx .B →.W .W →.L EXTB Dx .B →.L 1 HALT ...
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... Freescale Semiconductor, Inc. Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax MOVEM #<list>,<ea-2>x .L <ea-2>y,#<list> .L MOVEQ #<data>,Dx .B → .L MSAC Ry,RxSF .L - (.W × .W) → (.L × .L) → .L MSACL Ry,RxSF,<ea-1>y, (.W × .W) → . (.L × .L) → .L, .L MULS <ea>y, → → .L MULU < ...
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... Freescale Semiconductor, Inc. Instruction Timing Table 2-7. User-Mode Instruction Set Summary (Continued) Instruction Operand Syntax TST <ea>y UNLK Ax WDDATA <ea> default the HALT instruction is a supervisor-mode instruction; however, it can be configured to allow user-mode execution by setting CSR[UHE]. Table 2-8 describes supervisor-mode instructions. ...
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... Freescale Semiconductor, Inc. certain hardware resources within the processor are marked as “busy” for two clock cycles after the final DSOC cycle of the store instruction subsequent store instruction is encountered within this two-cycle window stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive store operations is two cycles. • ...
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... Freescale Semiconductor, Inc. Instruction Timing Table 2-10 lists execution times for MOVE.{B,W} instructions. Table 2-10. Move Byte and Word Execution Times Source Rx (Ax) Dy 1(0/0) 1(0/1) Ay 1(0/0) 1(0/1) (Ay) 4(1/0) 4(1/1) (Ay)+ 4(1/0) 4(1/1) -(Ay) 4(1/0) 4(1/1) (d16,Ay) 4(1/0) 4(1/1) (d8,Ay,Xi*SF) 5(1/0) 5(1/1) (xxx).w ...
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... Freescale Semiconductor, Inc. in the MAC execution pipeline. Table 2-12. MAC Move Execution Times Opcode Í Rn move.l <ea>,ACC 1(0/0) move.l <ea>,MACSR 2(0/0) move.l <ea>,MASK 1(0/0) move.l ACC,Rx 3(0/0) move.l MACSR,CCR 3(0/0) move.l MACSR,Rx 3(0/0) move.l MASK,Rx 3(0/0) 2.7.2 Execution Timings—One-Operand Instructions Table 2-13 shows standard timings for single-operand instructions ...
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... Freescale Semiconductor, Inc. Instruction Timing Table 2-14. Two-Operand Instruction Execution Times Opcode Í Rn add.l <ea>,Rx 1(0/0) add.l Dy,<ea> — addi.l #imm,Dx 1(0/0) addq.l #imm,<ea> 1(0/0) addx.l Dy,Dx 1(0/0) and.l <ea>,Rx 1(0/0) and.l Dy,<ea> — andi.l #imm,Dx 1(0/0) asl.l <ea>,Dx 1(0/0) asr.l < ...
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... Freescale Semiconductor, Inc. Table 2-14. Two-Operand Instruction Execution Times (Continued) Opcode Í Rn mac.l Ry,Rx,ea,Rw — moveq #imm,Dx — msac.w Ry,Rx,ea,Rw — msac.l Ry,Rx,ea,Rw — muls.w <ea>,Dx 3(0/0) mulu.w <ea>,Dx 3(0/0) muls.l <ea>,Dx 5(0/0) mulu.l <ea>,Dx 5(0/0) or.l <ea>,Rx 1(0/0) or.l Dy,<ea> ...
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... Freescale Semiconductor, Inc. Instruction Timing Table 2-15. Miscellaneous Instruction Execution Times (Continued) Opcode Í Rn nop 3(0/0) pea Í — 2(0/1) pulse 1(0/0) stop #imm — trap #imm — trapf 1(0/0) trapf.w 1(0/0) trapf.l 1(0/0) unlk Ax 3(1/0) wddata.l Í — 7(1/0) wdebug.l Í ...
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... Freescale Semiconductor, Inc. if bcc is a forward branch && CCR[ then the bcc is predicted as taken else if bcc is a backward branch then the bcc is predicted as taken Table 2-17 shows timing for Bcc instructions. Table 2-17. Bcc Instruction Execution Times Opcode Correctly as Taken bcc 2 ...
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... Freescale Semiconductor, Inc. Exception Processing Overview fixed-length stack frame for all exceptions. The exception type determines whether the program counter in the exception stack frame defines the address of the faulting instruction (fault the next instruction to be executed (next). 4. The processor acquires the address of the first instruction of the exception handler. ...
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... Freescale Semiconductor, Inc. Table 2-18. Exception Vector Assignments (Continued) Vector Numbers Vector Offset (Hex) 62–63 0F8–0FC 64–255 100–3FC 1 The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PC of the instruction that immediately follows the instruction that caused the fault. ...
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... Freescale Semiconductor, Inc. Exception Processing Overview Table 2-20. Fault Status Encodings FS[3–0] 0000 Not an access or address error 0001-001x Reserved 0100 Error on instruction fetch 0101–011x Reserved 1000 Error on operand write 1001 Attempted write to write-protected space 101x Reserved 1100 Error on operand read 1101– ...
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... Freescale Semiconductor, Inc. Table 2-21. MCF5307 Exceptions (Continued) Exception Trace ColdFire processors provide instruction-by-instruction tracing. While the processor is in trace mode Exception (SR[T] = 1), instruction completion signals a trace exception. This allows a debugger to monitor program execution. The only exception to this definition is the STOP instruction. If the processor is in trace mode, the instruction before the STOP executes and then generates a trace exception ...
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... Freescale Semiconductor, Inc. Exception Processing Overview Table 2-21. MCF5307 Exceptions (Continued) Exception Reset Asserting the reset input signal (RSTI) causes a reset exception. Reset has the highest exception Exception priority; it provides for system initialization and recovery from catastrophic failure. When assertion of RSTI is recognized, current processing is aborted and cannot be recovered. The reset exception places the processor in supervisor mode by setting SR[S] and disables tracing by clearing SR[T]. This exception also clears SR[M] and sets the processor’ ...
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... Freescale Semiconductor, Inc. Chapter 3 Hardware Multiply/Accumulate (MAC) Unit This chapter describes the MCF5307 multiply/accumulate (MAC) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). 3.1 Overview The MAC unit provides hardware support for a limited set of digital signal processing (DSP) operations used in embedded code, while supporting the integer multiply instructions in the ColdFire microprocessor family ...
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... Freescale Semiconductor, Inc. Overview Figure 3-1. ColdFire MAC Multiplication and Accumulation The MAC unit is an extension of the basic multiplier found on most microprocessors. It can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application constraints. For example, small digital filters can tolerate some variance in the execution time of the algorithm ...
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... Freescale Semiconductor, Inc. These registers are described as follows: • Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations. • Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands from memory useful in the implementation of circular queues in operand memory. • ...
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... Freescale Semiconductor, Inc. Overview during the calculations. The need to move large amounts of data quickly can limit throughput in DSP engines. However, data can be moved efficiently by using the MOVEM instruction, which automatically generates line-sized burst references and is ideal for filling registers quickly with input data, filter coefficients, and output data. Loading an operand from memory into a register during a MAC operation makes some DSP operations, especially fi ...
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... Freescale Semiconductor, Inc. • Two’s complement signed integer: In this format, an N-bit operand represents a number within the range -2 of the least significant bit. • Two’s complement unsigned integer: In this format, an N-bit operand represents a number within the range 0 < operand < 2 least signifi ...
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... Freescale Semiconductor, Inc. MAC Instruction Execution Timings Table 3-3 shows standard timings for MAC move instructions. Table 3-3. MAC Move Instruction Execution Times Opcode Í Rn move.l <ea>,ACC 1(0/0) move.l <ea>,MACSR 6(0/0) move.l <ea>,MASK 5(0/0) move.l ACC,Rx 1(0/0) move.l ...
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... Freescale Semiconductor, Inc. Chapter 4 Local Memory This chapter describes the MCF5307 implementation of the ColdFire Version 3 local memory specification. It consists of two major sections. • Section 4.2, “SRAM Overview,” describes the MCF5307 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization ...
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... Freescale Semiconductor, Inc. SRAM Operation 0-modulo-32K location in the 4-Gbyte address space and configured to respond to either instruction or data accesses.Time-critical functions can be mapped into instruction the system stack. Other heavily-referenced data can be mapped into memory. The following summarizes features of the MCF5307 SRAM implementation: • ...
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... Freescale Semiconductor, Inc. Accesses are attempted in the following order: 1. SRAM 2. Cache (if space is defined as cacheable) 3. External access 4.4 SRAM Programming Model The SRAM programming model consists of RAMBAR. 4.4.1 SRAM Base Address Register (RAMBAR) The SRAM modules are configured through the RAMBAR, shown in Figure 4-1. ...
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... Freescale Semiconductor, Inc. SRAM Initialization Table 4-1. RAMBAR Field Description (Continued) Bits Name 5–1 C/I, Address space masks (ASn). These fields allow certain types of accesses to be masked, or SC, inhibited from accessing the SRAM module. These bits are useful for power management as SD, described in Section 4.6, “ ...
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... Freescale Semiconductor, Inc. out of internal SRAM or cache during DMA access. The ColdFire processor or an external emulator using the debug module can perform these initialization functions. 4.5.1 SRAM Initialization Code The code segment below initializes the SRAM. The code sets the base address of the SRAM at 0x2000_0000 and then initializes the RAM to zeros ...
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... Freescale Semiconductor, Inc. Power Management move.l 24(a7),d4 asr.l #4,d4 .align 4 loop: movem.l (a0),#0xf movem.l #0xf,(a1) lea.l 16(a0),a0 lea.l 16(a1),a1 subq.l #1,d4 bne.b loop movem.l (a7),#0x1c lea.l 12(a7),a7 rts 4.6 Power Management Because processor memory references may be simultaneously sent to an SRAM module and cache, power can be minimized by confi ...
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... Freescale Semiconductor, Inc. Control ColdFire Processor Directory Array Core Data Address Address Path Figure 4-2. Unified Cache Organization The cache supports operation of copyback, write-through, or cache-inhibited modes. The cache lock feature can be used to guarantee deterministic response for critical code or data areas. A nonblocking cache services read hits or write hits from the processor while a fill (caused by a cache allocation progress ...
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... Freescale Semiconductor, Inc. Cache Organization Way 0 Set 0 Set 1 • • • Set 126 Set 127 TAG V M Where: TAG—21-bit address tag V—Valid bit for line M—Modified bit for line Figure 4-3. Cache Organization and Line Format A set is a group of four lines (one from each level, or way), corresponding to the same index into the cache array. 4.8.1 Cache Line States: Invalid, Valid-Unmodifi ...
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... Freescale Semiconductor, Inc. 4.8.2 The Cache at Start-Up As Figure 4-4 (A) shows, after power-up, cache contents are undefined; V and M may be set on some lines even though the cache may not contain the appropriate data for start up. Because reset and power-up do not invalidate cache lines automatically, the cache should be cleared explicitly by setting CACR[CINVA] before the cache is enabled (B). After the entire cache is fl ...
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... Freescale Semiconductor, Inc. Cache Organization Invalid ( Valid, not modified ( Valid, modified ( A:Cache population at B:Cache after invalidation, start-up before it is enabled Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Set 0 Set 127 At reset, cache contents Setting CACR[CINVA] are indeterminate; V and invalidates the entire M may be set ...
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... Freescale Semiconductor, Inc. 4.9 Cache Operation Figure 4-5 shows the general fl caching operation. Address 31 11 Tag Data/Tag Reference Set Select A[10:4] Address A[31:11] Figure 4-5. Caching Operation The following steps determine if a cache line is allocated for a given address: 1. The cache set index, A[10:4], selects one cache set. ...
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... Freescale Semiconductor, Inc. Cache Operation be deallocated and replaced. First the cache controller looks for an invalid line, with way 0 the highest priority. If all lines have valid data, a 2-bit replacement counter is used to choose the way. After a line is allocated, the pointer increments to point to the next way. ...
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... Freescale Semiconductor, Inc. Normally, cache-inhibited reads bypass the cache and are performed on the external bus. The exception to this normal operation occurs when all of the following conditions are true during a cache-inhibited read: • The cache-inhibited fill buffer bit, CACR[DNFB], is set. • The access is an instruction read. ...
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... Freescale Semiconductor, Inc. Cache Operation cache if matching data is found. Otherwise, the data is read from memory and the cache is updated. When a line is being read from memory for either a write-through or copyback read miss, the longword within the line that contains the core-requested data is loaded first and the requested data is given immediately to the processor, without waiting for the three remaining longwords to reach the cache ...
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... Freescale Semiconductor, Inc. 3. ACR1 access does not hit in the RAMBAR or the ACRs, the default is provided for all accesses in CACR. Cache-inhibited write accesses bypass the cache and a corresponding external write is performed. Cache-inhibited reads bypass the cache and are performed on the external bus, except when all of the following conditions are true: • ...
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... Freescale Semiconductor, Inc. Cache Operation 4.9.3.2 Write Miss The cache controller handles processor writes that miss in the cache differently for write-through and copyback regions. Write misses to copyback regions cause the cache line to be read from system memory, as shown in Figure 4-6. 1. Writing character X to 0x0B generates a write miss. Data cannot be written to an invalid line. ...
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... Freescale Semiconductor, Inc. also written to external memory. The cache line state is unchanged. For copyback accesses, the cache controller updates the cache line and sets the M bit for the line. An external write is not performed and the cache line state changes to (or remains in) the modified state. ...
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... Freescale Semiconductor, Inc. Cache Operation 4.9.5.2 Cache Pushes Cache pushes occur for line replacement and as required for the execution of the CPUSHL instruction. To reduce the requested data’s latency in the new line, the modified line being replaced is temporarily placed in the push buffer while the new line is fetched from memory. After the bus transfer for the new line completes, the modifi ...
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... Freescale Semiconductor, Inc. another cache fill is required (for example, cache miss to process) during the continued instruction execution by the processor pipeline, the pipeline stalls until the push and store buffers are empty, then generate the required external bus transaction. Supervisor instructions, the NOP instruction, and exception processing synchronize the processor core and guarantee the push and store buffers are empty before proceeding ...
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... Freescale Semiconductor, Inc. Cache Operation Invalid ( Valid, not modified ( Valid, modified ( A:Ways 0 and 1 are filled. B:CACR[DHLCK] is set, Ways 2 and 3 are locking ways 0 and 1. invalid. Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Set 0 Set 127 After reset, the cache is After CACR[HLCK] is ...
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... Freescale Semiconductor, Inc. 4.10 Cache Registers This section describes the MCF5307 implementation of the Version 3 cache registers. 4.10.1 Cache Control Register (CACR) The CACR in Figure 4-8 contains bits for configuring the cache. It can be written by the MOVEC register instruction and can be read or written from the debug facility. A hardware reset clears CACR, which disables the cache ...
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... Freescale Semiconductor, Inc. Cache Registers Table 4-4. CACR Field Descriptions (Continued) Bits Name 27 HLCK Half-cache lock mode 0 Normal operation. The cache allocates the lowest invalid way. If all ways are valid, the cache allocates the way pointed at by the counter and then increments this counter modulo-4. ...
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... Freescale Semiconductor, Inc. The SIM MBAR region should be mapped as cache-inhibited through an ACR Field Address Base Reset Uninitialized R/W Rc Figure 4-9. Access Control Register Format (ACRn) Table 4-5 describes ACRn fields. I Table 4-5. ACRn Field Descriptions Bits Name 31–24 Address Address base. Compared with address bits A[31:24]. Eligible addresses that match are base assigned the access control attributes of this register ...
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... Freescale Semiconductor, Inc. Cache Management 4.11 Cache Management The cache can be enabled and configured by using a MOVEC instruction to access CACR. A hardware reset clears CACR, disabling the cache and removing all configuration information; however, reset does not affect the tags, state information, and data in the cache. ...
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... Freescale Semiconductor, Inc. move.l d0,a0 cmpi.l #4,d0 bne setloop rts The following CACR loads assume the default cache mode is copyback. CacheLoadAndLock: move.l #0xA1000100,d0; enable and invalidate cache ... movec d0,cacr ; ... in the CACR The following code preloads half of the cache (4 Kbytes). It assumes a contiguous block of data mapped into the cache, starting at a 0-modulo-4K address ...
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... Freescale Semiconductor, Inc. Cache Operation Summary Figure 4-11 shows the three possible cache line states and possible processor-initiated transitions for memory configured as copyback. Transitions are labeled with a capital letter indicating the previous state and a number indicating the specific case listed in Table 4-11. ...
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... Freescale Semiconductor, Inc. Table 4-6. Cache Line State Transitions Access Invalid ( Read (C,W)I1 Read line from miss memory and update cache; supply data to processor valid state. Read hit (C,W)I2 Not possible. Write CI3 Read line from miss memory and update (copy- cache ...
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... Freescale Semiconductor, Inc. Cache Operation Summary The following tables present the same information as Table 4-6, organized by the current state of the cache line. In Table 4-7 the current state is invalid. Table 4-7. Cache Line State Transitions (Current State Invalid) Access Read miss Read hit ...
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... Freescale Semiconductor, Inc. In the current state is modified. Table 4-9. Cache Line State Transitions (Current State Modified) Access Read miss CD1 Push modified line to buffer; read new line from memory and update cache; supply data to processor; write push buffer contents to memory; ...
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... Freescale Semiconductor, Inc. Cache Initialization Code 4-30 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 5 Debug Support This chapter describes the Revision B enhanced hardware debug support in the MC5307. This revision of the ColdFire debug architecture encompasses the earlier revision. 5.1 Overview The debug module is shown in Figure 5-1. ColdFire CPU Core Debug Module Control ...
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... Freescale Semiconductor, Inc. Signal Description The Version 2 ColdFire core implemented the original debug architecture, now called Revision A. Based on feedback from customers and third-party developers, enhancements have been added to succeeding generations of ColdFire cores. The Version 3 core implements Revision B of the debug architecture, providing more flexibility for configuring the hardware breakpoint trigger registers and removing the restrictions involving concurrent BDM processing while hardware breakpoint registers are active ...
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... Freescale Semiconductor, Inc. Figure 5-2 shows PSTCLK timing with respect to PST and DDATA. PSTCLK PST DDATA or 5.3 Real-Time Trace Support Real-time trace, which defines the dynamic execution path fundamental debug function. The ColdFire solution is to include a parallel output port providing encoded processor status and data to an external development system ...
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... Freescale Semiconductor, Inc. Real-Time Trace Support Table 5-2. Processor Status Encoding PST[3:0] Hex Binary 0x0 0000 Continue execution. Many instructions execute in one processor cycle instruction requires more clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding. 0x1 0001 Begin execution of one instruction. For most instructions, this encoding signals the fi ...
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... Freescale Semiconductor, Inc. Bytes are displayed in least-to-most-significant order. The processor captures only those target addresses associated with taken branches which use a variant addressing mode, that is, RTE and RTS instructions, JMP and JSR instructions using address register indirect or indexed addressing modes, and all exception vectors. ...
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... Freescale Semiconductor, Inc. Programming Model programming model by executing the WDEBUG instruction. Thus, the breakpoint hardware in the debug module can be accessed by the external development system using the debug serial interface or by the operating system running on the processor core. Software is responsible for guaranteeing that accesses to these resources are serialized and logically consistent ...
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... Freescale Semiconductor, Inc. Table 5-3. BDM/Breakpoint Registers DRc[4–0] Register Name 0x00 Configuration/status register 0x01–0x04 Reserved 0x05 BDM address attribute register 0x06 Address attribute trigger register 0x07 Trigger definition register 0x08 Program counter breakpoint register 0x09 Program counter breakpoint mask register 0x0A– ...
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... Freescale Semiconductor, Inc. Programming Model Table 5-4. AATR Field Descriptions Bits Name 15 RM Read/write mask. Setting RM masks R in address comparisons. 14–13 SZM Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons. 12–11 TTM Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons. ...
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... Freescale Semiconductor, Inc. 31 Field Reset R/W Write only. ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG instruction and via the BDM port using the ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and via the BDM port using the WDMREG DRc[4– ...
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... Freescale Semiconductor, Inc. Programming Model Table 5-7. BAAR Field Descriptions Bits Name 7 R Read/write 0 Write 1 Read 6–5 SZ Size 00 Longword 01 Byte 10 Word 11 Reserved 4–3 TT Transfer type. See the TT definition in Table 5-4. 2–0 TM Transfer modifier. See the TM definition in Table 5-4. ...
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... Freescale Semiconductor, Inc. Table 5-8. CSR Field Descriptions Bit Name 31–28 BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. BSTAT is cleared by a TDR write CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled. ...
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... Freescale Semiconductor, Inc. Programming Model Table 5-8. CSR Field Descriptions (Continued) Bit Name 10 UHE User halt enable. Selects the CPU privilege level required to execute the HALT instruction. 0 HALT is a supervisor-only instruction. 1 HALT is a supervisor/user instruction. 9–8 BTB Branch target bytes. Defines the number of bytes of branch target address DDATA displays. ...
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... Freescale Semiconductor, Inc. Table 5-9 describes DBR fields. Table 5-9. DBR Field Descriptions Bits Name 31–0 Data Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a breakpoint trigger. Table 5-10 describes DBMR fields. ...
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... Freescale Semiconductor, Inc. Programming Model 31 Field Reset R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the RDMREG Set Descriptions.” DRc[4–0] Figure 5-10. Program Counter Breakpoint Register (PBR) Table 5-12 describes PBR fields. ...
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... Freescale Semiconductor, Inc. The debug module has no hardware interlocks prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR (by clearing TDR[29,13] before defining triggers. A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. Section Table 5-14., “TDR Field Descriptions,” describes how to handle multiple breakpoint conditions ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) Table 5-14. TDR Field Descriptions (Continued) Bits Name 28–22 EDx Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement 12–6 on the processor’s local data bus. Clearing all EDx bits disables data breakpoints. ...
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... Freescale Semiconductor, Inc hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of BKPT. This type of halt is always first made pending in the processor. Next, the processor samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point. See Section 5.6.1, “ ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) DSI must meet the required input setup and hold timings and the DSO is specifi delay relative to the rising edge of the processor clock. See Table 5-1. The development system serves as the serial communication channel master and must generate DSCLK. ...
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... Freescale Semiconductor, Inc. 5.5.2.1 Receive Packet Format The basic receive packet, Figure 5-14, consists of 16 data bits and 1 status bit Figure 5-14. Receive BDM Packet Table 5-15 describes receive BDM packet fields. Table 5-15. Receive BDM Packet Field Description Bits Name ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) Table 5-17. BDM Command Summary Command Mnemonic Read A/D / Read the selected address or data register and RAREG register return the results through the serial interface. RDREG Write A/D / Write the data operand to the specified address or ...
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... Freescale Semiconductor, Inc. 15 Operation Figure 5-16. BDM Command Format Table 5-18 describes BDM fields. Table 5-18. BDM Field Descriptions Bit Name 15–10 Operation Specifies the command. These values are listed in Table 5-17 Reserved 8 R/W Direction of operand transfer. 0 Data is written to the CPU or to memory from the development system. ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) COMMANDS TRANSMITTED TO THE DEBUG MODULE COMMAND CODE TRANSMITTED DURING THIS CYCLE HIGH-ORDER 16 BITS OF MEMORY ADDRESS READ (LONG) MS ADDR ??? "NOT READY" XXX "ILLEGAL" SEQUENCE TAKEN IF ILLEGAL COMMAND IS RECEIVED BY DEBUG MODULE RESULTS FROM PREVIOUS COMMAND RESPONSES FROM THE DEBUG MODULE Figure 5-17 ...
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... Freescale Semiconductor, Inc. • Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is sent to the debug module during the fi ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.1 Read A/D Register ( Read the selected address or data register and return the 32-bit result. A bus error response is returned if the CPU core is not halted. Command/Result Formats Command 0x2 Result Figure 5-18. Command Sequence: RAREG/RDREG ??? Figure 5-19 ...
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... Freescale Semiconductor, Inc. 5.5.3.3.2 Write A/D Register ( The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format 0x2 Figure 5-20. Command Sequence WDREG/WAREG ??? Figure 5-21 ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.3 Read Memory Location ( Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. ...
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... Freescale Semiconductor, Inc. 5.5.3.3.4 Write Memory Location ( Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) Command Sequence: WRITE (B/W) MS ADDR ??? "NOT READY" WRITE (LONG) MS ADDR ??? "NOT READY" Figure 5-25. Operand Data This two-operand instruction requires a longword absolute address that specifies a location to which the data operand written. Byte data is sent as a 16-bit word, justified in the LSB; 16- and 32-bit ...
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... Freescale Semiconductor, Inc. 5.5.3.3.5 Dump Memory Block ( is used with the command to access large blocks of memory. An initial DUMP READ is executed to set up the starting address of the block and to retrieve the first result initial is not executed before the first READ The command retrieves subsequent operands. The initial address is incremented by DUMP the operand size ( and saved in a temporary register ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) Command Sequence: DUMP (B/W) ??? DUMP (LONG) ??? Figure 5-27. Operand Data: None Result Data: Requested data is returned as either a word or longword. Byte data is returned in the least-significant byte of a word result. Word results return 16 bits of significant data; longword results return 32 bits. A value of 0x0001 (with S set) is returned if a bus error occurs ...
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... Freescale Semiconductor, Inc. 5.5.3.3.6 Fill Memory Block ( A command is used with the FILL initial is executed to set up the starting address of the block and to supply the first WRITE operand. The command writes subsequent operands. The initial address is incremented FILL by the operand size ( and saved in a temporary register after the memory write. ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) Command Sequence: FILL (LONG) FILL (B/W) MS DATA ??? "NOT READY" XXX "ILLEGAL" FILL (LONG) FILL (B/W) DATA ??? "NOT READY" XXX "ILLEGAL" Figure 5-29. Operand Data: A single operand is data to be written to the memory location. Byte data is sent as a 16-bit word, justified in the least-significant byte; 16- and 32-bit operands are sent as 16 and 32 bits, respectively ...
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... Freescale Semiconductor, Inc. 5.5.3.3.7 Resume Execution ( The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.8 No Operation ( performs no operation and may be used as a null command where required. NOP Command Formats 0x0 Figure 5-32. Command Sequence: Figure 5-33. Operand Data: None Result Data: The command-complete response, 0xFFFF (with S cleared), is returned during the next shift operation. ...
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... Freescale Semiconductor, Inc. 5.5.3.3.9 Synchronize PC to the PST/DDATA Lines ( The _ command captures the current PC and displays it on the PST/DDATA SYNC PC outputs. After the debug module receives the command, it sends a signal to the ColdFire processor that the current PC must be displayed. The processor then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of CSR[BTB]. The specifi ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.10 Read Control Register ( Read the selected control register and return the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specifi ...
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... Freescale Semiconductor, Inc. 5.5.3.3.11 Write Control Register ( The operand (longword) data is written to the specified control register. The write alters all 32 register bits. Command/Result Formats Command 0x2 0x0 0x0 Result Figure 5-38. Command Sequence: WCREG EXT WORD MS ADDR ??? "NOT READY" Figure 5-39. ...
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... Freescale Semiconductor, Inc. Background Debug Mode (BDM) 5.5.3.3.12 Read Debug Module Register ( Read the selected debug module register and return the 32-bit result. The only valid register selection for the command is CSR (DRc = 0x00). Note that this read of the CSR RDMREG clears the trigger status bits (CSR[BSTAT]) if either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled ...
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... Freescale Semiconductor, Inc. 5.5.3.3.13 Write Debug Module Register ( The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction. ...
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... Freescale Semiconductor, Inc. Real-Time Debug Support 5.6.1 Theory of Operation Breakpoint hardware can be configured to respond to triggers in several ways. The response desired is programmed into TDR. As shown in Table 5-21, when a breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status, operands, or branch addresses. ...
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... Freescale Semiconductor, Inc. fetches a unique exception vector, 12, from the vector table. Execution continues at the instruction address in the vector corresponding to the breakpoint triggered. All interrupts are ignored while the processor is in emulator mode. The debug interrupt handler can use supervisor instructions to save the necessary context such as the state of all program-visible registers into a reserved memory area ...
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... Freescale Semiconductor, Inc. Motorola-Recommended BDM Pinout • Read/write address and data registers • Read/write control registers For BDM commands that access memory, the debug module requests the processor’s local bus. The processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access ...
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... Freescale Semiconductor, Inc. The CSR provides capabilities to display operands based on reference type (read, write, or both). Additionally, for certain change-of-flow branch instructions, another CSR field provides the capability to display {0x2, 0x3, 0x4} bytes of the target instruction address. For both situations, an optional PST value {0x8, 0x9, 0xB} provides the marker identifying the size and presence of valid data on the DDATA output ...
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... Freescale Semiconductor, Inc. Processor Status, DDATA Definition Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax cmp.l <ea>y,Rx cmpi.l #imm,Dx divs.l <ea>y,Dx divs.w <ea>y,Dx divu.l <ea>y,Dx divu.w <ea>y,Dx eor.l Dy,<ea>x eori.l #imm,Dx ext.l Dx ext.w Dx extb.l Dx jmp <ea>x jsr <ea>x lea < ...
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... Freescale Semiconductor, Inc. Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax movem.l #list,<ea>x PST = 0x1, {PST = 0xB destination},... movem.l <ea>y,#list PST = 0x1, {PST = 0xB source},... moveq #imm,Dx PST = 0x1 msac.l Ry,Rx PST = 0x1 msac.l Ry,Rx,ea,Rw PST = 0x1, {PST = 0xB source}, {PST = 0xB destination} msac ...
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... Freescale Semiconductor, Inc. Processor Status, DDATA Definition Table 5-22. PST/DDATA Specification for User-Mode Instructions (Continued) Instruction Operand Syntax unlk Ax wddata.b <ea>y wddata.l <ea>y wddata.w <ea>y 1 For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An), (d8,An,Xi), (d8,PC,Xi) ...
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... Freescale Semiconductor, Inc. Table 5-23. PST/DDATA Specification for Supervisor-Mode Instructions Instruction Operand Syntax movec Ry,Rc rte stop #imm wdebug <ea>y The move-to-SR and RTE instructions include an optional PST = 0x3 value, indicating an entry into user mode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode, a multiple-cycle status of 0xD is signaled ...
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... Freescale Semiconductor, Inc. Processor Status, DDATA Definition 5-48 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. System Integration Module (SIM) Intended Audience Part II is intended for users who need to understand the interface between the ColdFire core processor complex, described in Part I, and internal peripheral devices, described in Part III. It includes a general description of the SIM and individual chapters that describe components of the SIM, such as the phase-lock loop (PLL) timing source, interrupt controller for both on-chip and external peripherals, confi ...
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... Freescale Semiconductor, Inc. includes a description of signals involved in DRAM operations. The remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. Suggested Reading The following literature may be helpful with respect to the topics in Part II: 2 • The I C Bus Specification, Version 2.1 (January 2000) Acronyms and Abbreviations Table II-i contains acronyms and abbreviations are used in Part II ...
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... Freescale Semiconductor, Inc. Table II-i. Acronyms and Abbreviated Terms (Continued) Term NOP No operation PCLK Processor clock PLL Phase-locked loop POR Power-on reset Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter Part II ...
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... Freescale Semiconductor, Inc. II-iv For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 6 SIM Overview This chapter provides detailed operation information regarding the system integration module (SIM). It describes the SIM programming model, bus arbitration, and system-protection functions for the MCF5307. 6.1 Features The SIM, shown in Figure 6-1, provides overall control of the bus and serves as the interface between the ColdFire core processor complex and the internal peripheral devices ...
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... Freescale Semiconductor, Inc. Features The following is a list of the key SIM features: • Module base address register (MBAR) — Base address location of all internal peripherals and SIM resources — Address space masking to internal peripherals and SIM resources • Phase-locked loop (PLL) clock control register (PLLCR) for CPU STOP instruction — ...
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... Freescale Semiconductor, Inc. 6.2 Programming Model The following sections describe the registers incorporated into the SIM. 6.2.1 SIM Register Memory Map Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM are memory-mapped registers offset from the MBAR address pointer defined in MBAR[BA]. This supervisor-level register is described in Section 6.2.2, “ ...
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... Freescale Semiconductor, Inc. Programming Model Table 6-1. SIM Registers (Continued) MBAR [31:24] Offset 0x04C Software watchdog timer (ICR0) [p. 9-3] 0x050 UART0 (ICR4) [p. 9-3] 0x054 DMA2 (ICR8) [p. 9-3] 6.2.2 Module Base Address Register (MBAR) The supervisor-level MBAR, Figure 6-2, specifies the base address and allowable access types for all internal peripherals written with a MOVEC instruction using the CPU address 0xC0F. (See the ColdFire Family Programmer’ ...
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... Freescale Semiconductor, Inc. Table 6-2 describes MBAR fields. Table 6-2. MBAR Field Descriptions Bits Field 31–12 BA Base address. Defines the base address for a 4-Kbyte address range. 11–9 — Reserved, should be cleared Write protect. Mask bit for write cycles in the MBAR-mapped register address range. ...
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... Freescale Semiconductor, Inc. Programming Model Table 6-3 describes RSR fields. Table 6-3. RSR Field Descriptions Bits Name 7 HRST Hardware or system reset 1 An external device driving RSTI caused the last reset. Assertion of reset by an external device causes the core processor to take a reset exception. All registers in internal peripherals and the SIM are reset ...
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... Freescale Semiconductor, Inc. Code enables software watchdog timer interrupt and SWTA functionality by writing SYPCR. Problem: 1. Watchdog timer times out due to unterminated bus Software watchdog timer IRQ Timeout 2. Watchdog timer interrupt cannot be serviced due to hung bus cycle. Wait for another timeout before setting SYPCR[SWTA]. ...
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... Freescale Semiconductor, Inc. Programming Model 1. Disable the software watchdog timer by clearing SYPCR[SWE]. 2. Reset the counter by writing 0x55 and then 0xAA to SWSR. 3. Update SYPCR[SWT,SWP]. 4. Reenable the watchdog timer by setting SYPCR[SWE]. This can be done in step 3. 6.2.5 System Protection Control Register (SYPCR) The SYPCR, Figure 6-5, controls the software watchdog timer, timeout periods, and software watchdog timer transfer acknowledge ...
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... Freescale Semiconductor, Inc. Table 6-4. SYPCR Field Descriptions (Continued) Bits Name 2 SWTA Software watchdog transfer acknowledge enable 0 SWTA transfer acknowledge disabled 1 SWTA asserts transfer acknowledge enabled. After one timeout period of the unacknowledged assertion of the software watchdog timer interrupt, the software watchdog transfer acknowledge asserts, which allows the watchdog timer to terminate a bus cycle and allow the IACK to occur ...
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... Freescale Semiconductor, Inc. Programming Model 6.2.8 PLL Clock Control for CPU STOP Instruction The SIM contains the PLL clock control register, which is described in detail in Section 7.2.4, “PLL Control Register (PLLCR).” PLLCR[ENBSTOP,PLLIPL] are significant to the operation of the SIM, and are described as follows: • ...
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... Freescale Semiconductor, Inc. 6.2.10 Bus Arbitration Control This section describes the bus arbitration register and the four arbitration schemes. 6.2.10.1 Default Bus Master Park Register (MPARK) The MPARK, shown in Figure 6-9, determines the default bus master arbitration between internal transfers (core and DMA module) and between internal and external transfers to internal resources ...
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... Freescale Semiconductor, Inc. Programming Model Table 6-6. MPARK Field Descriptions (Continued) Bits Name 3 SHOWDATA Enable internal register data bus to be driven on external bus. EARBCTRL must be set for this function to work. Section 6.2.10.1.2, “Arbitration between Internal and External Masters for Accessing Internal Resources,” describes the proper use of SHOWDATA. ...
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... Freescale Semiconductor, Inc. Note that the internal DMA has higher priority than the core if the internal DMA has its bandwidth BWC bits set to 000 (maximum bandwidth). • Park on master core priority (PARK = 01)—The core retains bus mastership as long as it needs it. After it negates its internal bus request, the core does not have to rearbitrate for the bus unless the DMA module has requested the bus when it is idle ...
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... Freescale Semiconductor, Inc. Programming Model • Park on current master priority (PARK = 11)—The current bus master retains mastership as long as it needs the bus. The other device can become the bus master only when the bus is idle. For example, if the core is bus master out of reset, it retains mastership as long as it needs the bus ...
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... Freescale Semiconductor, Inc. memories from responding to internal register transfers that go to the external bus. The AS signal and all chip-select-related strobe signals are not asserted. Do not immediately follow a cycle in which SHOWDATA is set with a cycle using fast termination. • In multiple-master systems, disabling arbitration with EARBCTRL allows performance improvement because internal register bus transfer cycles do not interfere with the external bus ...
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... Freescale Semiconductor, Inc. Programming Model 6-16 For More Information On This Product, MCF5307 User’s Manual Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Chapter 7 Phase-Locked Loop (PLL) This chapter describes configuration and operation of the phase-locked loop (PLL) module. It describes in detail the registers and signals that support the PLL implementation. 7.1 Overview The basic features of the MCF5307 PLL implementation are as follows: • ...
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... Freescale Semiconductor, Inc. PLL Operation 7.1.1 PLL:PCLK Ratios The specifications for the clocks in the PLL module are summarized in Table 0-1. Table 0-1. PLL Clock Specifications Symbol Description — PLL lock time CLKIN Input clock PCLK Internal processor clock 33.34 MHz ...
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... Freescale Semiconductor, Inc. 7.2.4 PLL Control Register (PLLCR) The PLL control register (PLLCR), Figure 7-2, provides control over the PLL Field ENBSTOP Reset R/W Address Figure 7-2. PLL Control Register (PLLCR) Table 7-1 describes PLLCR bits. Table 7-1. PLLCR Field Descriptions ...
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... Freescale Semiconductor, Inc. Timing Relationships Table 7-2. PLL Module Input SIgnals SIgnal FREQ[1:0] Input bus indicating the CLKIN frequency range. FREQ[1:0] are multiplexed with D[3:2] and are sampled while RSTI is asserted. FREQ[1:0] must be correctly set for proper operation. These signals do not affect CLKIN frequency but are required to set up the analog PLL to handle the input clock frequency. – ...