TWR-56F8257 Freescale Semiconductor, TWR-56F8257 Datasheet - Page 37

• Manufacturer Part Number: TWR-56F8257
• Description: TOWER SYSTEM KIT MC56F8257
• Manufacturer: Freescale Semiconductor
• Type: DSC, Digital Signal Controllerr

Specifications of TWR-56F8257

• Contents: Board, Cables, Documentation, DVD
• For Use With/related Products: Freescale Tower System, MC56F8257
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Each of these sources has an associated bit in the reset status register (RSTAT) in the system integration module (SIM).
The external pin reset function is shared with a GPIO port A7 on the RESET/GPIOA7 pin. The reset function is enabled
following any reset of the device. Bit 7 of the GPIOA_PER register must be cleared to use this pin as a GPIO port pin. When
the pin is enabled as the RESET pin, an internal pullup device is automatically enabled.
5.4
The on-chip clock synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an
external clock to run 56F8000 family devices at user-selectable frequencies up to 60 MHz.
The features of OCCS module include:
The clock generation module provides the programming interface for the PLL, internal relaxation oscillator, and crystal
oscillator. It also provides a postscaler to divide clock frequency down by 1, 2, 4, 8, 16, 32, 64, 128, or 256 before feeding it to
the SIM. The SIM is responsible for further dividing these frequencies by 2, which ensures a 50% duty cycle in the system clock
output. For details, refer to the OCCS section of the device’s reference manual.
5.4.1
When an external frequency source or crystal is not used, an internal relaxation oscillator can supply the reference frequency.
It is optimized for accuracy and programmability while providing several power-saving configurations that accommodate
different operating conditions. The internal relaxation oscillator has little temperature and voltage variability. To optimize
power, the internal relaxation oscillator supports a run state (8 MHz), standby state (400 kHz), and a power-down state.
During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the PLLCR word is set to 0).
Application code can then also switch to the external clock source and power down the internal oscillator, if desired. If a
changeover between internal and external clock sources is required at power-on, ensure that the clock source is not switched
until the desired external clock source is enabled and stable.
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally
adjusted to within + 0.078% of 8 MHz by trimming an internal capacitor. Bits 0–9 of the oscillator control (OSCTL) register
allow you to set an additional offset (trim) to this preset value to increase or decrease capacitance. Each unit added or subtracted
changes the output frequency by about 0.078% of 8 MHz, allowing incremental adjustment until the desired frequency accuracy
is achieved.
The center frequency of the internal oscillator is calibrated at the factory to 8 MHz, and the TRIM value is stored in the flash
information block and loaded to the HFM IFR option register 0 at reset. When using the relaxation oscillator, the boot code
should read the HFM IFR option register 0 and set this value as OSCTL TRIM. For further information, refer to the device’s
reference manual.
5.4.2
The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in the frequency range,
specified for the external crystal, of 4 MHz to 16 MHz. A ceramic resonator can be substituted for the 4 MHz to 16 MHz range.
When used to supply a source to the internal PLL, the recommended crystal/resonator is in the 8 MHz to 16 MHz range to
optimize PLL performance. Oscillator circuits appear in
Freescale Semiconductor
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Software reset (SWR)
Ability to power down the internal relaxation oscillator or crystal oscillator
Ability to put the internal relaxation oscillator into standby mode
Ability to power down the PLL
Provides a 2x system clock that operates at two times the system clock to the timer and SCI modules
Safety shutdown feature if the PLL reference clock is lost
Ability to be driven from an external clock source
On-chip Clock Synthesis
Internal Clock Source
Crystal Oscillator/Ceramic Resonator
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Figure 9
and
Figure
10.
Follow the crystal supplier’s recommendations
General System Control Information
37