SI4021-A1-FT Silicon Laboratories Inc, SI4021-A1-FT Datasheet



Manufacturer Part Number
Silicon Laboratories Inc

Specifications of SI4021-A1-FT

Package / Case
433MHz, 868MHz, 915MHz
Modulation Or Protocol
Data Rate - Maximum
Power - Output
Current - Transmitting
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
2.2 V ~ 5.4 V
Operating Temperature
-40°C ~ 85°C
Operating Frequency
433 MHz to 915 MHz
Mounting Style
Operating Supply Voltage
2.2 V to 5.4 V
Supply Current
1.5 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names

Available stocks

Part Number
Part Number:
5 000
Si4021 Universal ISM
Band FSK Transmitter
Silicon Labs’ Si4021 is a single chip, low power, multi-channel FSK
transmitter designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the 433, 868, and 915 MHz bands.
Used in conjunction with Si4020, Silicon Labs’ FSK receiver, the Si4021
transmitter features EZRadio TM technology, which produces a flexible, low
cost, and highly integrated solution that does not require production
alignments. All required RF functions are integrated. Only an external
crystal and bypass filtering are needed for operation. The Si4021 builds on
the features presented by the Si4020 by offering a higher output power
and an improved phase noise characteristic. The Si4021 shares the same
pinout and control command set as the Si4020. The Si4021 offers all of
the frequencies as the Si4020, with the exception of the 315 MHz band.
The Si4021 features a completely integrated PLL for easy RF design, and
its rapid settling time allows for fast frequency hopping, bypassing
multipath fading and interference to achieve robust wireless links. In
addition, highly stable and accurate FSK modulation is accomplished by
direct closed-loop modulation with bit rates up to 115.2 kbps. The PLL’s
high resolution allows the use of multiple channels in any of the bands.
The integrated power amplifier of the transmitter has an open-collector
differential output that directly drive a loop antenna with programmable
output level. No additional matching network is required. An automatic
antenna tuning circuit is built in to avoid costly trimming procedures and
de-tuning due to the “hand effect”.
For low-power applications, the device supports automatic activation from
sleep mode. Active mode can be initiated by several wake-up events (on-
chip timer timeout, low supply voltage detection, or activation of any of the
four push-button inputs).
The Si4021’s on-chip digital interface supports both a microcontroller
mode and an EEPROM mode. The latter allows complete data transmitter
operation without a microcontroller (both control commands and data are
read from the EEPROM). Any wake-up event can start a transmission of the
corresponding data stored in the EEPROM.
Si4021-DS Rev 2.3r 0408
 Fully integrated (low BOM, easy design-in)
 No alignment required in production
 Fast settling, programmable, high-resolution PLL
 Fast frequency hopping capability
 Stable and accurate FSK modulation with programmable
 Programmable PLL loop bandwidth
 Direct loop antenna drive
 Automatic antenna tuning circuit
 Programmable output power level
 Alternative OOK support
 EEPROM mode supported
 SPI bus for applications with microcontroller
 Clock output for microcontroller
 Integrated programmable crystal load capacitor
 Multiple event handling options for wake-up activation
 Push-button event handling with switch de-bounce
 Wake-up timer
 Low battery detection
 2.2 to 5.4 V supply voltage
 Low power consumption
 Low standby current (0.3 µA)
 Compact 16-pin TSSOP package
 Transmit bit synchronization
 Remote control
 Home security and alarm
 Wireless keyboard/mouse and other PC peripherals
 Toy control
 Remote keyless entry
 Tire pressure monitoring
 Telemetry
 Personal/patient data logging
 Remote automatic meter reading
Microcontroller Mode
See for any applicable
errata. See back page for ordering information.
This document refers to Si4021-IC Rev A1.

SI4021-A1-FT Summary of contents

Page 1

... Si4020 by offering a higher output power and an improved phase noise characteristic. The Si4021 shares the same pinout and control command set as the Si4020. The Si4021 offers all of the frequencies as the Si4020, with the exception of the 315 MHz band. ...

Page 2

... DETAILED DESCRIPTION The Si4021 FSK transmitter is designed to cover the unlicensed frequency bands at 433, 868, and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. PLL The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. The PLL’ ...

Page 3

... Crystal connection (other terminal of crystal to VSS) Ground reference Connect to logic high (microcontroller mode) Power amplifier output (open collector) Power amplifier output (open collector) Interrupt request output for microcontroller (active low) and status read output Positive supply voltage Serial data input for FSK modulation Si4021 3 ...

Page 4

... GP2 GP8 CONTROLLER GP1 GP9 GP0 GP5 CLKin (EC osc. mode) GND OPTIONAL 100p 10p GND OPTIONAL SDI 1 2 SCK 3 nSEL 4 PB1 IA4221 5 PB2 6 PB3 7 PB4 8 CLK GND Si4021 Antenna 16 FSK 15 VDD 14 nIRQ 13 RFP 12 RFN 11 MOD 10 VSS 9 XTL X1 10MHz GND GND 4 ...

Page 5

... Data output of serial control interface Crystal connection (other terminal of crystal to VSS) Ground reference Connect to logic low (EEPROM mode) Power amplifier output (open collector) Power amplifier output (open collector) Low battery voltage detector output (active low) Positive supply voltage Not used, connect to VDD or VSS Si4021 5 ...

Page 6

... GND OPTIONAL GND C3 10p 1 8 nCS EEPROM 3 6 nWP 25A A 080 GND SDI SCK 3 14 nSEL 4 13 PB1 5 IA 4221 12 PB2 6 11 PB3 7 10 PB4 10MHz VCC HOLD SCK ntenna FSK VDD nLBD x RFP RFN MOD VSS GND GND Si4021 6 ...

Page 7

... Conditions/Notes 433 MHz band 868 MHz band 915 MHz band 433 MHz band 868 MHz band 915 MHz band All blocks disabled Only crystal oscillator is on Programmable in 0.1 V steps 5 Si4021 Max Units 1000 V ºC 125 ºC 260 Max Units 5 º ...

Page 8

... Programmable in 30 kHz steps Programmable in 0.5 pF steps, tolerance +/- 10% After V has reached 90% of final value dd Crystal ESR < 100 Ohms (Note 8) Crystal oscillator must be enabled to ensure proper calibration at startup (Note pure capacitive load Si4021 Min Typ Max Units MHz 430.24 439.75 860.48 879 ...

Page 9

... Using anything but a 10 MHz crystal is allowed but not recommended because all crystal-referred timing and frequency parameters will change accordingly. Note 3: Adjustable in 8 steps. Note 4: Optimal antenna admittance/impedance for the Si4021: 434 MHz 868 MHz 915 MHz Note 5: With selective resonant antennas (see: Application Notes available from ...

Page 10

... Mkr1 868.0010 MHz -12.2 dBm Ref 0 dBm Samp Log 10 dB/ VAvg 100 Span 2 MHz Center 915 MHz Sweep 40.74 ms (2001 pts) Res BW 10 kHz Si4021 Phase Noise L Mkr 1 1.00000 MHz Atten 0.00 dB -101.95 dBc/ Frequency Offset Type X Axis Spot Freq 1 MHz -101 ...

Page 11

... Span 2 MHz Center 868 MHz Sweep 4.074 s (2000 pts) #Res BW 1 kHz Antenna Tuning Characteristics  Mkr1 19.98 MHz -44. Span 50 MHz Sweep 45.47 s (2000 pts) Si4021 At 868 MHz with Atten 20 dB Span 2 MHz #VBW 1 kHz Sweep 4.074 s (2000 pts) 750–970 MHz 11 ...

Page 12

... Data setup time (SDI transition to SCK rising edge Data hold time (SCK rising edge to SDI transition Data delay time OD t Push-button input low time BL Timing Diagram t SS nSEL SCK BIT15 BIT14 BIT13 SDI nIRQ t OD BIT8 BIT7 BIT1 POR WK-UP Si4021 Minimum value [ns SHI t SH BIT0 nIRQ 12 ...

Page 13

... M is the three bit binary number <m2 : m0> SIGN = (ms) XOR (FSK input) Note:  Use range from Si4021 Related control bits x0, ms a0, ex, es, ea, eb, et, dc f11 ook dwc, ebs p4 d0 b1, ...

Page 14

... For processing the events caused by the peripheral blocks (POR, LBD, wake-up timer, push-buttons) the chip requires operation of the crystal oscillator. This operation is fully controlled internally, independently from the status of the ex bit, but if the dc bit is zero, the oscillator remains active until Sleep Command is issued. (This command can be considered as an event controller reset.) Oscillator control logic POR C000h Si4021 14 ...

Page 15

... POR p1 p0 B0h 0 The output power is given in the table as relative to the -3 maximum available power, which depends on the actual -6 antenna impedance. (See: Antenna Application Note -9 available from POR A7D0h Band [MHz 433 1 43 868 2 43 915 POR C800h Si4021 15 ...

Page 16

... Stops the crystal oscillator after S periods of the microcontroller clock (if a1=1 and ex=0) to enable the microcontroller to execute all necessary commands before entering sleep mode itself. The 8-bit value S is determined by bits <s7 : s0> dwc 0 ebs t4 of the detector POR C200h POR C410h Si4021 16 ...

Page 17

... With the addition of this feature, there is a way to build a device that uses 3 buttons, but performs 4 functions.  possible to detect multiple pressed push-buttons, in both modes. In EEPROM mode the controller executes sequentially all the routines belonging to the pressed buttons POR CA00h Si4021 17 ...

Page 18

... Status rd Status rd POR, LBD, WAKE UP TIMER, P. BUTTONS EVENT FLAGS VDD CLR filter To Digital glitch filter for Push-button4 Si4021 PB2 PB1 Status rd Note: *PB_nIRQdly is equal with the debounce time Notice: Only one EVENT is serviced simultaneously the others are pending. EVENT FLAG SLEEP Command * STAT ...

Page 19

... In EEPROM mode, when N bytes have been read and transmitted the controller continues reading the EEPROM and processing the data as control commands. This process stops after Sleep Command has been read from the EEPROM POR E000h POR time, to switch on. The actual value sx startup time. Valid data can be transmitted only when sp Si4021 19 ...

Page 20

... This mode is not SPI compatible, therefore it is not recommended in microcontroller mode.  If the crystal oscillator and the PLL are running, the delay is not needed xtal osc. stable synthesizer on, PLL locked, PA ready to transmit NOTE: * See page 6 for the timing values Si4021 20 ...

Page 21

... Bit 1 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For more detailed description see the Reset modes section POR PB1 PB2 bw1 bw0 0 0 Charge pump current [dBc/Hz] (typical) -112 25% -110 33% -107 50% -102 100 POR status out PB3 PB4 LBD WK-UP nIRQ POR D200h Si4021 21 ...

Page 22

... Related Control Command Remarks Crystal– Synthesizer – Power Amplifier auto Power Management on/off mode enable Push Button Continuous execution for all push buttons Bit Rate BR=10M/29/(35+1)~9600 bps Sleep Power down Si4021 22 ...

Page 23

... AFC Control Command (bit 0 Related Control Command 872 Configuration Control 610 Frequency 60 Data Transmit 00 Sleep Remarks 433MHz band, Xtal C =12pF L f =90kHz dev f =(43+1552/4000)*10MHz c Transmit the next 96 bytes Data Power down address 80 Si4021 23 ...

Page 24

... CRYSTAL SELECTION GUIDELINES The crystal oscillator of the Si4021 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can variety of crystal types can be used. ...

Page 25

... Si4021 has a rising 25 ...

Page 26

... Issuing FE00h command will trigger software reset. See the Wake-up Timer Command. Reset ramp line (100mV/ms) Reset ramp line (100mV/ms) ramp start.. Typical example when a switch-mode regulator is used to supply the radio, dd line. Follow the manufacturer’s recommendations how to decrease the ripple of the regulator IC time time Si4021 26 ...

Page 27

... Osc_On (In terna Status rd Slee p cmd Tclk_tail** Debouncing Time + Status rd cmd Stat. b its (PB x) Tsx* Status rd cmd Stat. b its (PB x) 1us Tsx* Status rd Slee p cmd Tclk_tail te: * Tsx : Crystal oscillator st artup Length of Tclk_tail is determined by the parameter in the Sleep comm a nd Si4021 27 ...

Page 28

... C4 must be connected parallel to the supply decoupling capacitors (10nF + 2.2µF recommended) as close as possible to the VDD and VSS pins C1 [pF] L3 [nH] L4 [nH] (Note 1) 390 16 3.3 100 5.1 2 100 4 [pF] C2 [pF] C3 [pF] (Note 2) 3.3 6.0 2.7 1.5 2.2 1.2 1.8 2.2 1.2 Si4021 C4 [pF] (Note 3) 220 ...

Page 29

... Important: The bytes of the data stream should follow each other continuously, otherwise the clock recovery circuit of the receiver side will be unable to track. Further details of packet structures can be found in the IA ISM-UGSB1 software development kit manual Databytes (received in the FIFO of the receive r) Synchron pattern Si4021 the picture above) will be the first 0 29 ...

Page 30

... EXAMPLE APPLICATIONS For Microcontroller Mode Schematic PCB Layout of Keyboard Transmitter Demo Circuit Using Microcontroller Mode (operating in the 915 MHz band) Top Layer Si4021 IA4221 Bottom Layer 30 ...

Page 31

... For EEPROM Mode Schematic PCB Layout of Push-Button Transmitter Demo Circuit Using EEPROM Mode (operating in the 434 MHz band) Top Layer Si4021 Bottom Layer 31 ...

Page 32

... 6.40 BSC. 4,40 4,50 0,169 0,60 0,75 0,020 1.00 REF REF. 12 REF. Gauge Plane 0.25 Detail “A” Dimensions in Inches Nom. Max 0,035 0,041 0,009 0,010 0,197 0,201 0.252 BSC. 0,173 0,177 0,024 0,030 0.39 REF REF. 12 REF. Si4021 32 ...

Page 33

... This page has been intentionally left blank. Si4021 33 ...

Page 34

... RELATED PRODUCTS AND DOCUMENTS Si4021 Universal ISM Band FSK Transmitter DESCRIPTION Si4021 16-pin TSSOP die Demo Boards and Development Kits DESCRIPTION Development Kit Remote Temp. Monitoring Station Related Resources DESCRIPTION Antenna Selection Guide Antenna Development Guide IA4320 Universal ISM Band FSK Receiver Note: Volume orders must include chip revision to be accepted ...

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