SI4021-A1-FT Silicon Laboratories Inc, SI4021-A1-FT Datasheet - Page 29

• Manufacturer Part Number: SI4021-A1-FT
• Description: IC TX FSK 915MHZ 5.4V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4021-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 433MHz, 868MHz, 915MHz
• Modulation Or Protocol: FSK, OOK
• Data Rate - Maximum: 512kbps
• Power - Output: 8dBm
• Current - Transmitting: 24mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.2 V ~ 5.4 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 433 MHz to 915 MHz
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.2 V to 5.4 V
• Supply Current: 1.5 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Applications: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1622-5

Si4021
EXAMPLE APPLICATIONS: DATA PACKET TRANSMISSION
Data packet structure
An example data packet structure using the IA422x – IA4320 pair for data transmission. This packet structure is an example of how to use
the high efficiency FIFO mode at the receiver side:
D
D
D
. . .
D
AA AA AA 2D D4
0
1
2
N
Prea mble
Databytes (received in the
FIFO of the receive r)
Synchron pattern
The first 3 bytes compose a 24 bit length ‘01’ pattern to let enough time for the clock recovery of the receiver to lock. The next two bytes
compose a 16 bit synchron pattern which is essential for the receiver’s FIFO to find the byte synchron in the received bit stream. The
synchron patters is followed by the payload. The first byte transmitted after the synchron pattern (D
in the picture above) will be the first
0
received byte in the FIFO.
Important: The bytes of the data stream should follow each other continuously, otherwise the clock recovery circuit of the receiver side will
be unable to track.
Further details of packet structures can be found in the IA ISM-UGSB1 software development kit manual.
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