A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet

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A3P1000L-PQG208

Manufacturer Part Number
A3P1000L-PQG208
Description
FPGA - Field Programmable Gate Array 1M SYSTEM GATES
Manufacturer
Actel
Datasheet

Specifications of A3P1000L-PQG208

Processor Series
A3P1000
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
154
Data Ram Size
147456
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
1 M
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3P1000L-PQG208
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P1000L-PQG208
Manufacturer:
Microsemi Corporation
Quantity:
341
Part Number:
A3P1000L-PQG208I
Manufacturer:
Microsemi Corporation
Quantity:
345
February 2009
© 2010 Actel Corporation
ProASIC3L Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
High Capacity
Reprogrammable Flash Technology
High Performance
In-System Programming (ISP) and Security
High-Performance Routing Hierarchy
Advanced and Pro (Professional) I/Os
Table 1 • ProASIC3 Low-Power Product Family
ProASIC3L Devices
ARM Cortex-M1 Devices
System Gates
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Kbits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Maximum User I/Os
Package Pins
Notes:
1. Refer to the
2. AES is not available for ARM Cortex-M1 ProASIC3L devices.
3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.
• Dramatic Reduction in Dynamic and Static Power Savings
• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power
• Low Power Consumption in Flash*Freeze Mode Allows for
• Supports Single-Voltage System Operation
• Low-Impedance Switches
• 250,000 to 3,000,000 System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System
• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
• FlashLock
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
• 700 Mbps DDR, LVDS-Capable I/Os
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
VQFP
PQFP
FBGA
Instantaneous Entry to / Exit from Low-Power Flash*Freeze
Mode
Process
Performance
PCI (1.2 V systems)
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
®
to Secure FPGA Contents
Cortex-M1
2
3
1
product brief for more information.
FG144, FG256
A3P250L
250,000
VQ100
PQ208
6,144
Yes
157
36
18
8
1
1
4
FG144, FG256, FG484
M1A3P600L
A3P600L
600,000
PQ208
13,824
108
Yes
235
24
18
1
1
4
Clock Conditioning Circuit (CCC) and PLL
SRAMs and FIFOs
ARM
• Single-Ended
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
• Wide Range Power Supply Voltage Support per JESD8-B,
• Wide Range Power Supply Voltage Support per JESD8-12,
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os Programmable Output
• Programmable Input Delay (A3PE3000L only)
• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC
• Six CCC Blocks, One with Integrated PLL (ProASIC3L) and All
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
• ARM Cortex™-M1 Soft Processor Available with or without
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
M-LVDS
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (A3PE3000L only)
Allowing I/Os to Operate from 2.7 V to 3.6 V
Allowing I/Os to Operate from 1.14 V to 1.575 V
Slew Rate and Drive Strength
(except PQ208)
with Integrated PLL (ProASIC3EL)
and External Feedback
systems) and 350 MHz (1.5 V systems))
and ×18 organizations available)
Operation:
– 250 MHz: For 1.2 V systems
– 350 MHz: For 1.5 V systems
Debug
®
Processor Support in ProASIC3L FPGAs
FG144, FG256, FG484
M1A3P1000L
I/O
A3P1000L
1,000,000
PQ208
24,576
144
300
Yes
32
18
1
1
4
Standards:
LVTTL,
FG324, FG484, FG896
M1A3PE3000L
A3PE3000L
3,000,000
LVCMOS
PQ208
75,264
504
620
112
Yes
Revision 9
18
1
6
8
®
3L Family
3
3.3 V /
®
I

A3P1000L-PQG208 Summary of contents

Page 1

... Yes Yes 157 235 PQ208 FG144, FG256, FG484 Revision 9 I/O Standards: LVTTL, LVCMOS ® A3P1000L A3PE3000L M1A3P1000L M1A3PE3000L 1,000,000 3,000,000 24,576 75,264 144 504 32 112 1 1 Yes Yes 300 620 PQ208 PQ208 FG144, FG256, FG484 FG324, FG484, FG896 ® ...

Page 2

... Table 2 • ProASIC3L FPGAs Package Sizes Dimensions Package VQ100 Length × Width 14 × 14 (mm\mm) Nominal Area 196 2 (mm ) Pitch (mm) 0.5 Height (mm) 1. A3P600L A3P1000L M1A3P600L M1A3P1000L I/O Type Single- Differential Single- 4 Ended I/O I/O Pairs Ended I/O – – 154 35 154 177 43 177 – ...

Page 3

... Speed Grade Blank = Standard 1 = 15% Faster than Standard Part Number ProASIC3L Devices A3P250L = 250,000 System Gates A3P600L = 600,000 System Gates A3P1000L = 1,000,000 System Gates A3PE3000L = 3,000,000 System Gates ProASIC3L Devices with Cortex-M1 M1A3P600L = 600,000 System Gates M1A3P1000L = 1,000,000 System Gates M1A3PE3000L = ...

Page 4

... C = Commercial temperature range: 0°C to 70°C ambient temperature Industrial temperature range: –40°C to 85°C ambient temperature. http://www.actel.com/contact/default.aspx A3P250L A3P600L M1A3P600L C, I – – – – – – Std. ✓ ✓ A3P1000L A3PE3000L M1A3P1000L M1A3PE3000L – – – –1 ✓ ✓ ...

Page 5

... FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 ProASIC3L Low Power Flash FPGAs ...

Page 6

...

Page 7

... ARM Cortex-M1 is available for free from Actel for use in M1 ProASIC3L FPGAs. The ARM-enabled devices have Actel ordering numbers that begin with M1 and do not support AES decryption. Flash*Freeze Technology The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which allows instantaneous switching from an active state to a static state ...

Page 8

... This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based ProASIC3L devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based ProASIC3L devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs ...

Page 9

... The versatility of the ProASIC3L core tile, as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable, allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming ...

Page 10

... RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Flash*Freeze Charge Technology Pumps CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600L and A3P1000L) ...

Page 11

... Flash*Freeze Technology The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which enables designers to instantaneously shut off dynamic power consumption while retaining all SRAM and register information. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption ...

Page 12

... Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents ...

Page 13

... Wide Range I/O Support Actel ProASIC3L devices support JEDEC-defined wide range I/O operation. ProASIC3L devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1. ...

Page 14

...

Page 15

ProASIC3L DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the ...

Page 16

ProASIC3L DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions Symbol T Ambient temperature A T Junction Temperature J 2 VCC 1.2 V–1.5 V wide range core voltage VJTAG JTAG DC voltage 3 VPUMP Programming voltage 6 VCCPLL Analog ...

Page 17

Table 2-4 • Overshoot and Undershoot Limits Average VCCI–GND Overshoot or Undershoot VCCI Duration as a Percentage of Clock Cycle 2 less 3 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at junction temperature at ...

Page 18

... ProASIC3L DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see 2 on page 2-5 for more details) ...

Page 19

VCC = VCCI + VT where VT can be from 0. 0.9 V (typically 0. VCC = 1.575 V Region 1: I/O Buffers are OFF VCC = 1.14 V Region 2: I/O buffers are ON. ...

Page 20

... A3P250L 256 12.0 38.6 A3P600L 256 8.5 32.0 A3P1000L 256 6.6 28.1 AGLE3000 324 TBD TBD A3P600L 484 9.5 27.5 A3P1000L 484 8.0 23.3 A3PE3000L 484 4.7 20.6 A3PE3000L 896 2.4 13 Table 2-5. 100°C 70°C – = ------------------------------------ = 1.463 W 20.5° ...

Page 21

... A3PE3000L Units 2. DC6 A3P1000L A3PE3000L Units 1.7 1.7 µA 1.8 1.8 µA 1.9 1.9 µA 2.2 2.2 µA 2.5 2.5 µA and P ). DC6 DC7 Units 0 µ ...

Page 22

... V / 1.5 V 1.7 1.7 1 1.5 V 1.8 1.8 1 1.5 V 1.9 1.9 1 1.5 V 2.2 2.2 1 1.5 V 2.5 2.5 and add I CCI and P ). DC6 DC7 A3P1000L A3PE3000L Units 0.88 2. 1.7 1.7 µA 1.8 1.8 µA 1.9 1.9 µA 2.2 2.2 µA 2.5 2.5 µA contribution. ...

Page 23

Power per I/O Pin Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Pro I/O Banks Single-Ended 3.3 V LVTTL/LVCMOS 3.3 V LVTTL/LVCMOS – Schmitt trigger 2.5 V LVCMOS 2.5 V ...

Page 24

ProASIC3L DC and Switching Characteristics Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS ...

Page 25

Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Pro I/Os Single-Ended 3.3 V LVTTL/LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS 3.3 V PCI ...

Page 26

ProASIC3L DC and Switching Characteristics Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS ...

Page 27

... AC13 * For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Libero IDE. ProASIC3L Low Power Flash FPGAs Device Specific Dynamic Power (µW/MHz) A3PE3000L A3P1000L A3P600L A3P250L 12.61 9.28 2.66 1.59 0.56 0.07 ...

Page 28

... For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Libero IDE Device Specific Dynamic Power (µW/MHz) Definition A3PE3000L A3P1000L A3P600L A3P250L Device Specific Dynamic Power (µW) Definition A3PE3000L A3P1000L A3P600L A3P250L See See See R e visio n 9 19.7 14.50 12.80 11 ...

Page 29

... Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: • The number of PLLs as well as the number and the frequency of each output clock generated • ...

Page 30

ProASIC3L DC and Switching Characteristics Combinatorial Cells Contribution— C-CELL C-CELL N is the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in 1 page ...

Page 31

Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this means that this net switches at ...

Page 32

ProASIC3L DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Registered 1. LVPECL D Q (Applicable to Advanced I/O Banks only 0.24 ns ICLKQ t = 0.26 ns ISUD Input LVTTL Clock ...

Page 33

PY PAD t = MAX MAX(t DIN V trip PAD 50% Y GND t PY (R) DIN GND Figure 2-4 • Input Buffer Timing Model and Delays (example) t DIN CLK I/O Interface ...

Page 34

ProASIC3L DC and Switching Characteristics D CLK D From Array I/O Interface D DOUT PAD Figure 2-5 • Output Buffer Model and Delays (example DOUT Q DOUT t = MAX MAX(t DOUT t ...

Page 35

EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD Vtrip VOL D 50 EOUT (R) VCC 50% EOUT t ZLS PAD Vtrip VOL Figure ...

Page 36

ProASIC3L DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-22 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial ...

Page 37

Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Advanced I/O Banks Drive Slew Min. I/O Standard Strength Rate V 3.3 V LVTTL / 12 mA ...

Page 38

ProASIC3L DC and Switching Characteristics Table 2-25 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS ...

Page 39

Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-26 • Summary of AC Memory Points Input Reference Voltage Standard (V 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V ...

Page 40

ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-28 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T VCCI Pro I/O Banks Standard 3.3 V LVTTL / 12 mA High 3.3 V ...

Page 41

Table 2-29 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T Case VCCI Advanced I/O Banks I/O Standard 3.3 V LVTTL / 12 mA High 5pF 3.3 V LVCMOS 2.5 V LVCMOS 12 mA High ...

Page 42

ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T VCCI Pro I/O Banks Standard 3.3 V LVTTL / 12 mA High 3.3 V ...

Page 43

Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T VCCI Advanced I/O Banks I/O Standard 3.3 V LVTTL / 12 mA High 5pF 3.3 V LVCMOS 2.5 V LVCMOS 12 mA High 5 ...

Page 44

ProASIC3L DC and Switching Characteristics Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Commercial-Case Conditions: T VCCI = 3.0 V Standard Plus I/O Banks I/O Standard 3.3 V LVTTL / 12 mA 3.3 V LVCMOS ...

Page 45

... PULL-DOWN Drive Strength Per PCI/PCI-X specification IBIS models located ) / I OHspec ProASIC3L Low Power Flash FPGAs R PULL- (Ω) (Ω) 100 300 50 150 100 200 50 100 200 225 100 112 200 224 100 112 TBD TBD – 14 – 12 – 15 – the Actel website ...

Page 46

... IBIS models located OLspec O H spec R e visio PULL-DOWN PULL- (Ω) (Ω) 100 300 100 300 50 150 50 150 100 300 100 300 50 150 50 150 100 200 100 200 50 100 50 100 200 224 100 112 TBD TBD the Actel website at ...

Page 47

... IBIS models located spec ProASIC3L Low Power Flash FPGAs R R PULL-DOWN PULL- (Ω) (Ω) 100 300 100 300 50 150 50 150 100 200 100 200 50 100 50 100 25 50 200 225 100 112 200 224 100 112 TBD TBD 25 75 the Actel website ...

Page 48

ProASIC3L DC and Switching Characteristics Table 2-38 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values VCCI Min 1.2 V LVCMOS ...

Page 49

Table 2-39 • I/O Short Currents I OSH Applicable to Pro I/Os 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCIX 3.3 V GTL 2.5 V GTL ...

Page 50

ProASIC3L DC and Switching Characteristics Table 2-40 • I/O Short Currents I Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCI-X * ...

Page 51

Table 2-41 • I/O Short Currents I OSH Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI/PCI 100°C ...

Page 52

... The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. ...

Page 53

Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low voltage transistor–transistor Logic (LVTTL general-purpose standard (EIA/JESD) for 3.3 V applications. This standard uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V ...

Page 54

ProASIC3L DC and Switching Characteristics Table 2-47 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL Min. Max. Drive Strength –0.3 0.8 ...

Page 55

Timing Characteristics 1 Core Voltage Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t ...

Page 56

ProASIC3L DC and Switching Characteristics Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT ...

Page 57

Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. ...

Page 58

ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed ...

Page 59

Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.70 ...

Page 60

ProASIC3L DC and Switching Characteristics Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t ...

Page 61

V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-62 • Minimum and Maximum ...

Page 62

ProASIC3L DC and Switching Characteristics Table 2-64 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS VIL Drive Min. Max. Strength –0.3 0 –0.3 0.7 ...

Page 63

Timing Characteristics 1 Core Voltage Table 2-66 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade DOUT DP ...

Page 64

ProASIC3L DC and Switching Characteristics Table 2-68 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT 4 mA Std. 0.54 ...

Page 65

Table 2-70 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.54 5.27 –1 0.46 ...

Page 66

ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-72 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t t ...

Page 67

Table 2-74 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/Os Drive Speed Strength Grade t t DOUT Std. 0.70 5.79 –1 0.60 4.92 6 ...

Page 68

ProASIC3L DC and Switching Characteristics Table 2-76 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/Os Drive Speed Strength Grade t t DOUT 4 mA Std. 0.70 ...

Page 69

V LVCMOS Low-voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-78 • Minimum and ...

Page 70

ProASIC3L DC and Switching Characteristics Table 2-80 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS VIL Drive Min. Max. Strength –0.3 0.35 * VCCI 0.65 ...

Page 71

Timing Characteristics 1 Core Voltage Table 2-82 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade DOUT DP ...

Page 72

ProASIC3L DC and Switching Characteristics Table 2-84 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT 2 mA Std. 0.54 ...

Page 73

Table 2-86 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.54 7.21 –1 0.46 ...

Page 74

ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-88 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t t ...

Page 75

Table 2-90 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.70 7.77 –1 0.60 6.61 ...

Page 76

ProASIC3L DC and Switching Characteristics Table 2-92 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT 2 mA Std. ...

Page 77

V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-94 • Minimum ...

Page 78

ProASIC3L DC and Switching Characteristics Table 2-96 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS VIL Drive Min. Max. Strength –0.3 0.35 * VCCI 0.65 * ...

Page 79

Timing Characteristics 1 Core Voltage Table 2-98 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade DOUT DP ...

Page 80

ProASIC3L DC and Switching Characteristics Table 2-100 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT 2 mA Std. 0.54 ...

Page 81

Table 2-102 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.54 7.32 –1 0.46 ...

Page 82

ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-104 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t t ...

Page 83

Table 2-106 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.70 8.00 –1 0.60 6.80 ...

Page 84

ProASIC3L DC and Switching Characteristics Table 2-108 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Speed Strength Grade t t DOUT 2 mA Std. ...

Page 85

V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-110 • Minimum and Maximum DC ...

Page 86

ProASIC3L DC and Switching Characteristics Test Point Datapath Figure 2-11 • AC Loading Table 2-113 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low ( Measuring point = V See Table 2-26 on page 2-25 trip. 2- ...

Page 87

Timing Characteristics 1 Core Voltage Table 2-114 • 1.2 V LVCMOS Low Slew Commercial-Case Conditions: T Applicable to Pro I/O Banks Drive Speed Strength Grade t t DOUT Std. 0.77 11.80 0.05 2.38 –1 0.66 ...

Page 88

ProASIC3L DC and Switching Characteristics Table 2-119 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: T Applicable to Standard Plus I/O Banks Drive Strength Speed Grade Std. –1 Notes: 1. Software default selection highlighted in gray. 2. ...

Page 89

... Per PCI specification Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the database; Actel loadings for enable path characterization are described VCCI for ...

Page 90

ProASIC3L DC and Switching Characteristics Table 2-123 • 3.3 V PCI/PCI-X – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Advanced I/O Banks Speed Grade DOUT DP Std. 0.54 2.41 0.04 –1 0.46 ...

Page 91

Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-128 • Minimum and Maximum DC Input and Output Levels ...

Page 92

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-130 • 3.3 V GTL – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/O Banks Speed Grade ...

Page 93

V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-132 • Minimum and Maximum DC Input and Output Levels 2.5 GTL VIL ...

Page 94

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-134 • 2.5 V GTL – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 3.0 V VREF = 0.8 V Applicable to Pro I/O Banks Speed Grade ...

Page 95

V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-136 • Minimum and Maximum DC Input and Output Levels 3.3 V ...

Page 96

ProASIC3L DC and Switching Characteristics 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The V Table 2-140 • Minimum and Maximum DC Input ...

Page 97

Timing Characteristics Table 2-142 • 2.5 V GTL+ – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 2.3 V VREF = 1.0 V Applicable to Pro I/O Banks Speed Grade DOUT DP ...

Page 98

ProASIC3L DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-144 • ...

Page 99

Timing Characteristics Table 2-146 • HSTL Class I – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade DOUT DP ...

Page 100

ProASIC3L DC and Switching Characteristics HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-148 • ...

Page 101

Timing Characteristics Table 2-150 • HSTL Class II – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 1.4 V VREF = 0.75 V Applicable to Pro I/O Banks Speed Grade DOUT DP ...

Page 102

ProASIC3L DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-152 • Minimum and ...

Page 103

Timing Characteristics Table 2-154 • SSTL2 Class I – Applies to 1 Core Voltage Commercial-Case Conditions: T Worst-Case VCCI = 2.3 V VREF = 1.25 V Applicable to Pro I/Os Speed Grade DOUT DP DIN ...

Page 104

ProASIC3L DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-156 • Minimum and ...

Page 105

SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-160 • Minimum and Maximum DC Input and Output ...

Page 106

ProASIC3L DC and Switching Characteristics SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-164 • Minimum and ...

Page 107

... Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards ...

Page 108

ProASIC3L DC and Switching Characteristics Table 2-168 • Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH ODIFF V OCM V ...

Page 109

Timing Characteristics 1 Core Voltage Table 2-170 • LVDS – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Speed Grade t DOUT Std. 0.59 –1 0.50 Note: For specific junction temperature ...

Page 110

... These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in ...

Page 111

LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the ...

Page 112

ProASIC3L DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-176 • LVPECL – Applies to 1 Core Voltage Commercial-Case Conditions: T Applicable to Pro I/O Banks Speed Grade t DOUT Std. 0.59 –1 0.50 ...

Page 113

I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset PRE Data D C DFN1E1P1 E Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure 2-26 • ...

Page 114

ProASIC3L DC and Switching Characteristics Table 2-180 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...

Page 115

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D Data CC DFN1E1C1 E Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-27 • Timing Model of ...

Page 116

ProASIC3L DC and Switching Characteristics Table 2-181 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output ...

Page 117

Input Register 50% 50% CLK t ISUD 1 50% Data Enable 50% t IHE t ISUE Preset Clear Out_1 Figure 2-28 • Input Register Timing Diagram 50% 50% t IHD 0 50 IWPRE IRECPRE 50% 50 ...

Page 118

ProASIC3L DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-182 • Input Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Input Data Register ICLKQ t Data Setup Time for the Input Data ...

Page 119

Output Register 50% 50% CLK t 50% 1 Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-29 • Output Register Timing Diagram 50% 50% t OSUD OHD 0 50 OWPRE ORECPRE 50% 50 ...

Page 120

ProASIC3L DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-184 • Output Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data ...

Page 121

Output Enable Register 50% 50% CLK t OESUD 50% 1 D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT t Figure 2-30 • Output Enable Register Timing Diagram 50% 50% t OEHD 50 OEWPRE t OERECPRE 50% ...

Page 122

ProASIC3L DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-186 • Output Enable Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Enable Register OECLKQ t Data Setup Time for the Output Enable ...

Page 123

DDR Module Specifications Input DDR Module INBUF A Data B CLK CLKBUF C CLR INBUF Figure 2-31 • Input DDR Timing Model Table 2-188 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...

Page 124

ProASIC3L DC and Switching Characteristics CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-32 • Input DDR Timing Diagram Timing Characteristics 1 Core Voltage Table 2-189 • Input DDR Propagation Delays Commercial-Case ...

Page 125

V DC Core Voltage Table 2-190 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out Out_QR for Input DDR DDRICLKQ1 t Clock-to-Out Out_QF for Input DDR DDRICLKQ2 t Data Setup for Input DDR (fall) DDRISUD1 t Data ...

Page 126

ProASIC3L DC and Switching Characteristics Output DDR Module Data_F (from core) CLK CLKBUF Data_R (from core) CLR INBUF Figure 2-33 • Output DDR Timing Model Table 2-191 • Parameter Definitions Parameter Name t Clock-to-Out DDROCLKQ t Asynchronous Clear-to-Out DDROCLR2Q t ...

Page 127

CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-34 • Output DDR Timing Diagram Timing Characteristics 1 Core Voltage Table 2-192 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter ...

Page 128

ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-193 • Output DDR Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Out of DDR for Output DDR DDROCLKQ t Data_F Data Setup for Output DDR DDRISUD1 t Data_R Data ...

Page 129

VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the and ProASIC3 Macro ...

Page 130

ProASIC3L DC and Switching Characteristics OUT GND VCC OUT Figure 2-36 • Timing Model and Waveforms NAND2 or Any Combinatorial Logic MAX(t PD PD(RR) where edges are applicable ...

Page 131

Timing Characteristics 1 Core Voltage Table 2-194 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell Equation INV Y =!A AND2 · B NAND2 Y =!(A · B) OR2 ...

Page 132

ProASIC3L DC and Switching Characteristics VersaTile Specifications as a Sequential Module The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing ...

Page 133

CLK t SUD 50% Data EN 50 PRE SUE CLR Out t CLKQ Figure 2-38 • Timing Model and Waveforms Timing Characteristics 1 Core Voltage Table 2-196 • Register Delays Commercial-Case Conditions: T ...

Page 134

ProASIC3L DC and Switching Characteristics 1 Core Voltage Table 2-197 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Core Register CLKQ t Data Setup Time for the Core Register SUD t Data Hold Time for ...

Page 135

Global Resource Characteristics A3P250L Clock Tree Topology Clock delays are device-specific. global tree presented in Figure 2- used to drive all D-flip-flops in the device. CCC Figure 2-39 • Example of Global Tree Use in an A3P250L Device ...

Page 136

ProASIC3L DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the ...

Page 137

Table 2-200 • A3P600L Global Resource – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter Description t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High ...

Page 138

... Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to values. Table 2-203 • A3P1000L Global Resource – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t ...

Page 139

Table 2-204 • A3PE3000L Global Resource – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter Description t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High ...

Page 140

ProASIC3L DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-206 • ProASIC3LP CCC/PLL Specification CCC/PLL Operating at 1.2 V Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in ...

Page 141

Table 2-207 • ProASIC3LP CCC/PLL Specification CCC/PLL Operating at 1.5 V Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f 4 Serial Clock (SCLK) for Dynamic PLL Delay Increments in Programmable Delay Blocks Number of Programmable ...

Page 142

ProASIC3L DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-41 • RAM Models RAM4K9 RADDR8 ADDRA11 DOUTA8 RADDR7 DOUTA7 ADDRA10 ADDRA0 DOUTA0 RADDR0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA ...

Page 143

Timing Waveforms t CYC t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-42 • RAM Read for Pass-Through Output t CYC t CKH CLK ...

Page 144

ProASIC3L DC and Switching Characteristics CLK t AS ADD t BKS BLK_B t ENS WEN_B Figure 2-44 • RAM Write, Output Retained (WMODE = 0) CLK ADD BLK_B WEN_B (pass-through) DO (pipelined) Figure 2-45 ...

Page 145

CLK1 ADD1 DI1 1 t CCKH CLK2 WEN_B1 WEN_B2 A ADD2 0 DI2 D 0 DO2 D n (pass-through) DO2 D (pipelined) n Figure 2-46 • Write Access after ...

Page 146

ProASIC3L DC and Switching Characteristics CLK1 ADD1 DI1 CLK2 WEN_B1 WEN_B2 ADD2 DO2 (pass-through) DO2 (pipelined) Figure 2-47 • Read Access after Write onto Same Address ...

Page 147

CLK1 ADD1 A 0 WEN_B1 t CKQ1 DO1 D n (pass-through) DO1 D (pipelined CCKH CLK2 ADD2 A 0 DI2 D 1 WEN_B2 Figure 2-48 • Write Access after Read onto Same Address t ...

Page 148

ProASIC3L DC and Switching Characteristics Timing Characteristics Table 2-208 • RAM4K9 – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t ...

Page 149

Table 2-209 • RAM4K9 – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t BLK_B ...

Page 150

ProASIC3L DC and Switching Characteristics Table 2-210 • RAM512X18 – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B ...

Page 151

Table 2-211 • RAM512X18 – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input ...

Page 152

ProASIC3L DC and Switching Characteristics FIFO Figure 2-50 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 ...

Page 153

Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-51 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Assertion t ...

Page 154

ProASIC3L DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-53 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (Address Counter) (EMPTY) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY ...

Page 155

Timing Characteristics Table 2-212 • FIFO – Applies to 1 Core Voltage Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time ...

Page 156

ProASIC3L DC and Switching Characteristics Table 2-213 • FIFO – Applies to 1 Core Voltage Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t ...

Page 157

Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-56 • Timing Diagram Timing Characteristics Table 2-214 • Embedded FlashROM Access Time – Applies to 1 Core Voltage Commercial-Case Conditions: T Parameter t Address ...

Page 158

ProASIC3L DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the Characteristics" section ...

Page 159

... Package Pin Assignments 100-Pin VQFP 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC3L Low Power Flash FPGAs ...

Page 160

Package Pin Assignments 100-Pin VQFP Pin Number A3P250L Function 1 GND 2 GAA2/IO118UDB3 3 IO118VDB3 4 GAB2/IO117UDB3 5 IO117VDB3 6 GAC2/IO116UDB3 7 IO116VDB3 8 IO112PSB3 9 GND 10 GFB1/IO109PDB3 11 GFB0/IO109NDB3 12 VCOMPLF 13 GFA0/IO108NPB3 14 VCCPLF 15 GFA1/IO108PPB3 16 ...

Page 161

... PQFP 208 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. ProASIC3L Low Power Flash FPGAs 208-Pin PQFP ...

Page 162

Package Pin Assignments 208-Pin PQFP Pin Number A3PL250 Function 1 GND 2 GAA2/IO118UDB3 3 IO118VDB3 4 GAB2/IO117UDB3 5 IO117VDB3 6 GAC2/IO116UDB3 7 IO116VDB3 8 IO115UDB3 9 IO115VDB3 10 IO114UDB3 11 IO114VDB3 12 IO113PDB3 13 IO113NDB3 14 IO112PDB3 15 IO112NDB3 16 ...

Page 163

PQFP Pin Number A3PL250 Function 109 TRST 110 VJTAG 111 GDA0/IO60VDB1 112 GDA1/IO60UDB1 113 GDB0/IO59VDB1 114 GDB1/IO59UDB1 115 GDC0/IO58VDB1 116 GDC1/IO58UDB1 117 IO57VDB1 118 IO57UDB1 119 IO56NDB1 120 IO56PDB1 121 IO55RSB1 122 GND 123 VCCIB1 124 NC 125 NC ...

Page 164

Package Pin Assignments 208-Pin PQFP Pin Number A3PL600 Function 1 GND 2 GAA2/IO174PDB3 3 IO174NDB3 4 GAB2/IO173PDB3 5 IO173NDB3 6 GAC2/IO172PDB3 7 IO172NDB3 8 IO171PDB3 9 IO171NDB3 10 IO170PDB3 11 IO170NDB3 12 IO169PDB3 13 IO169NDB3 14 IO168PDB3 15 IO168NDB3 16 ...

Page 165

PQFP Pin Number A3PL600 Function 108 TDO 109 TRST 110 VJTAG 111 GDA0/IO88NDB1 112 GDA1/IO88PDB1 113 GDB0/IO87NDB1 114 GDB1/IO87PDB1 115 GDC0/IO86NDB1 116 GDC1/IO86PDB1 117 IO84NDB1 118 IO84PDB1 119 IO82NDB1 120 IO82PDB1 121 IO81PSB1 122 GND 123 VCCIB1 124 IO77NDB1 ...

Page 166

Package Pin Assignments 208-Pin PQFP Pin Number APL1000 Function 1 GND 2 GAA2/IO225PDB3 3 IO225NDB3 4 GAB2/IO224PDB3 5 IO224NDB3 6 GAC2/IO223PDB3 7 IO223NDB3 8 IO222PDB3 9 IO222NDB3 10 IO220PDB3 11 IO220NDB3 12 IO218PDB3 13 IO218NDB3 14 IO216PDB3 15 IO216NDB3 16 ...

Page 167

PQFP Pin Number APL1000 Function 108 TDO 109 TRST 110 VJTAG 111 GDA0/IO113NDB1 112 GDA1/IO113PDB1 113 GDB0/IO112NDB1 114 GDB1/IO112PDB1 115 GDC0/IO111NDB1 116 GDC1/IO111PDB1 117 IO109NDB1 118 IO109PDB1 119 IO106NDB1 120 IO106PDB1 121 IO104PSB1 122 GND 123 VCCIB1 124 IO99NDB1 ...

Page 168

Package Pin Assignments 208-Pin PQFP Pin A3PE3000L Number Function 1 GND 2 GNDQ 3 VMV7 4 GAB2/IO308PSB7V4 5 GAA2/IO309PDB7V4 6 IO309NDB7V4 7 GAC2/IO307PDB7V4 8 IO307NDB7V4 9 IO303PDB7V3 10 IO303NDB7V3 11 IO299PDB7V3 12 IO299NDB7V3 13 IO295PDB7V2 14 IO295NDB7V2 15 IO291PSB7V2 16 ...

Page 169

PQFP Pin A3PE3000L Number Function 106 VPUMP 107 GNDQ 108 TDO 109 TRST 110 VJTAG 111 VMV3 112 GDA0/IO153NPB3V4 113 GDB0/IO152NPB3V4 114 GDA1/IO153PPB3V4 115 GDB1/IO152PPB3V4 116 GDC0/IO151NDB3V4 117 GDC1/IO151PDB3V4 118 IO134NDB3V2 119 IO134PDB3V2 120 IO132NDB3V2 121 IO132PDB3V2 122 GND ...

Page 170

... Package Pin Assignments 144-Pin FBGA 12 11 Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner visio ...

Page 171

FBGA Pin Number A3P250L Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO16RSB0 A6 GND A7 IO29RSB0 A8 VCC A9 IO33RSB0 A10 GBA0/IO39RSB0 A11 GBA1/IO40RSB0 A12 GNDQ B1 GAB2/IO117UDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO14RSB0 ...

Page 172

Package Pin Assignments 144-Pin FBGA Pin Number A3P250L Function K1 GEB0/IO99NDB3 K2 GEA1/IO98PDB3 K3 GEA0/IO98NDB3 K4 GEA2/IO97RSB2 K5 IO90RSB2 K6 IO84RSB2 K7 GND K8 IO66RSB2 K9 GDC2/IO63RSB2 K10 GND K11 GDA0/IO60VDB1 K12 GDB0/IO59VDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO96RSB2 L4 ...

Page 173

FBGA Pin Number A3P600L Function A1 GNDQ A2 VMV0 A3 GAB0/IO02RSB0 A4 GAB1/IO03RSB0 A5 IO10RSB0 A6 GND A7 IO34RSB0 A8 VCC A9 IO50RSB0 A10 GBA0/IO58RSB0 A11 GBA1/IO59RSB0 A12 GNDQ B1 GAB2/IO173PDB3 B2 GND B3 GAA0/IO00RSB0 B4 GAA1/IO01RSB0 B5 IO13RSB0 ...

Page 174

Package Pin Assignments 144-Pin FBGA Pin Number A3P600L Function K1 GEB0/IO145NDB3 K2 GEA1/IO144PDB3 K3 GEA0/IO144NDB3 K4 GEA2/IO143RSB2 K5 IO119RSB2 K6 IO111RSB2 K7 GND K8 IO94RSB2 K9 GDC2/IO91RSB2 K10 GND K11 GDA0/IO88NDB1 K12 GDB0/IO87NDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO142RSB 2 ...

Page 175

... GFB0/IO208NPB3 F2 VCOMPLF F3 GFB1/IO208PPB3 F4 IO206NPB3 F5 GND F6 GND F7 GND F8 GCC0/IO91NDB1 F9 GCB0/IO92NPB1 F10 GND F11 GCA1/IO93PDB1 F12 GCA2/IO94PDB1 ProASIC3L Low Power Flash FPGAs 144-Pin FBGA Pin Number A3P1000L Function G1 GFA1/IO207PPB3 G2 GND G3 VCCPLF G4 GFA0/IO207NPB3 G5 GND G6 GND G7 GND G8 GDC1/IO111PPB1 G9 IO96NDB1 G10 GCC2/IO96PDB1 G11 IO95NDB1 G12 GCB2/IO95PDB1 H1 ...

Page 176

... GDB0/IO112NDB1 L1 GND L2 VMV3 L3 FF/GEB2/IO186RSB 2 L4 IO172RSB2 L5 VCCIB2 L6 IO153RSB2 L7 IO144RSB2 L8 IO140RSB2 L9 TMS L10 VJTAG L11 VMV2 L12 TRST M1 GNDQ M2 GEC2/IO185RSB2 M3 IO173RSB2 M4 IO168RSB2 M5 IO161RSB2 M6 IO156RSB2 M7 IO145RSB2 M8 IO141RSB2 M9 TDI M10 VCCIB2 3- 18 144-Pin FBGA Pin Number A3P1000L Function M11 VPUMP M12 GNDQ R e visio n 9 ...

Page 177

... FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ProASIC3L Low Power Flash FPGAs ...

Page 178

Package Pin Assignments 256-Pin FBGA Pin Number A3P250L Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO07RSB0 A6 IO10RSB0 A7 IO11RSB0 A8 IO15RSB0 A9 IO20RSB0 A10 IO25RSB0 A11 IO29RSB0 A12 IO33RSB0 A13 GBB1/IO38RSB0 A14 GBA0/IO39RSB0 A15 GBA1/IO40RSB0 A16 ...

Page 179

FBGA Pin Number A3P250L Function G13 GCC1/IO48PPB1 G14 IO47NPB1 G15 IO54PDB1 G16 IO54NDB1 H1 GFB0/IO109NPB3 H2 GFA0/IO108NDB3 H3 GFB1/IO109PPB3 H4 VCOMPLF H5 GFC0/IO110NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 GCC0/IO48NPB1 H13 GCB1/IO49PPB1 ...

Page 180

Package Pin Assignments 256-Pin FBGA Pin Number A3P250L Function P9 IO76RSB2 P10 IO71RSB2 P11 IO66RSB2 P12 NC P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO60VDB1 R1 GEA1/IO98PDB3 R2 GEA0/IO98NDB3 GEC2/IO95RSB2 R5 IO91RSB2 R6 IO88RSB2 R7 IO84RSB2 R8 ...

Page 181

FBGA Pin Number A3P600L Function A1 GND A2 GAA0/IO00RSB0 A3 GAA1/IO01RSB0 A4 GAB0/IO02RSB0 A5 IO11RSB0 A6 IO16RSB0 A7 IO18RSB0 A8 IO28RSB0 A9 IO34RSB0 A10 IO37RSB0 A11 IO41RSB0 A12 IO43RSB0 A13 GBB1/IO57RSB0 A14 GBA0/IO58RSB0 A15 GBA1/IO59RSB0 A16 GND B1 GAB2/IO173PDB3 ...

Page 182

Package Pin Assignments 256-Pin FBGA Pin Number A3P600L Function G13 GCC1/IO69PPB1 G14 IO65NPB1 G15 IO75PDB1 G16 IO75NDB1 H1 GFB0/IO163NPB3 H2 GFA0/IO162NDB3 H3 GFB1/IO163PPB3 H4 VCOMPLF H5 GFC0/IO164NPB3 H6 VCC H7 GND H8 GND H9 GND H10 GND H11 VCC H12 ...

Page 183

FBGA Pin Number A3P600L Function P9 IO107RSB2 P10 IO104RSB2 P11 IO97RSB2 P12 VMV1 P13 TCK P14 VPUMP P15 TRST P16 GDA0/IO88NDB1 R1 GEA1/IO144PDB3 R2 GEA0/IO144NDB3 R3 IO139RSB2 R4 GEC2/IO141RSB2 R5 IO132RSB2 R6 IO127RSB2 R7 IO121RSB2 R8 IO114RSB2 R9 IO109RSB2 ...

Page 184

... D14 GBB2/IO79PDB1 D15 IO79NDB1 D16 IO82NSB1 E1 IO217PDB3 E2 IO218PDB3 E3 IO221NDB3 E4 IO221PDB3 E5 VMV0 E6 VCCIB0 E7 VCCIB0 E8 IO38RSB0 R e visio n 9 256-Pin FBGA Pin Number A3P1000L Function E9 IO47RSB0 E10 VCCIB0 E11 VCCIB0 E12 VMV1 E13 GBC2/IO80PDB1 E14 IO83PPB1 E15 IO86PPB1 E16 IO87PDB1 F1 IO217NDB3 F2 IO218NDB3 F3 IO216PDB3 F4 ...

Page 185

... L12 VCCIB1 L13 GDB0/IO112NPB1 L14 IO106NDB1 L15 IO106PDB1 L16 IO107PDB1 M1 IO197NSB3 M2 IO196NPB3 M3 IO193NPB3 M4 GEC0/IO190NPB3 ProASIC3L Low Power Flash FPGAs 256-Pin FBGA Pin Number A3P1000L Function M5 VMV3 M6 VCCIB2 M7 VCCIB2 M8 IO147RSB2 M9 IO136RSB2 M10 VCCIB2 M11 VCCIB2 M12 VMV2 M13 IO110NDB1 M14 GDB1/IO112PPB1 M15 ...

Page 186

... R13 GDB2/IO115RSB2 R14 TDI R15 GNDQ R16 TDO T1 GND T2 IO183RSB2 T3 FF/GEB2/IO186RSB 2 T4 IO172RSB2 T5 IO170RSB2 T6 IO164RSB2 T7 IO158RSB2 T8 IO153RSB2 T9 IO142RSB2 T10 IO135RSB2 T11 IO130RSB2 3- 28 256-Pin FBGA Pin Number A3P1000L Function T12 GDC2/IO116RSB2 T13 IO120RSB2 T14 GDA2/IO114RSB2 T15 TMS T16 GND R e visio n 9 ...

Page 187

... FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. A1 Ball Pad Corner ProASIC3L Low Power Flash FPGAs ...

Page 188

Package Pin Assignments 324-Pin FBGA A3PE3000L Pin Number Function A1 GND A2 IO08NDB0V0 A3 IO08PDB0V0 A4 IO10NDB0V1 A5 IO10PDB0V1 A6 IO12PDB0V1 A7 GND A8 IO32NDB0V3 A9 IO32PDB0V3 A10 IO42PPB1V0 A11 IO52NPB1V1 A12 GND A13 IO66NDB1V3 A14 IO72NDB1V3 A15 IO72PDB1V3 A16 ...

Page 189

FBGA A3PE3000L Pin Number Function F12 IO58PDB1V2 F13 IO94PPB2V1 F14 VCOMPLB F15 GBC2/IO84PDB2V0 F16 IO84NDB2V0 F17 IO92NDB2V1 F18 IO92PDB2V1 G1 GND G2 IO287PDB7V1 G3 IO287NDB7V1 G4 IO283PPB7V1 G5 VCCIB7 G6 IO279PDB7V0 G7 IO291NPB7V2 G8 VCC G9 IO26NDB0V3 G10 IO34NDB0V4 ...

Page 190

Package Pin Assignments 324-Pin FBGA A3PE3000L Pin Number Function M9 IO192PPB4V4 M10 IO154NPB4V0 M11 VCC M12 GDA0/IO153NPB3V4 M13 IO132NDB3V2 M14 VCCIB3 M15 IO134NDB3V2 M16 IO134PDB3V2 M17 IO128PPB3V1 M18 GND N1 IO247NDB6V1 N2 IO247PDB6V1 N3 IO251NPB6V2 N4 GEC0/IO236NDB6V0 N5 VCOMPLE N6 ...

Page 191

FBGA A3PE3000L Pin Number Function V1 GND V2 IO218NDB5V3 V3 IO218PDB5V3 V4 IO206NDB5V1 V5 IO206PDB5V1 V6 IO198NPB5V0 V7 GND V8 IO190NDB4V4 V9 IO190PDB4V4 V10 IO182PPB4V3 V11 IO180PPB4V3 V12 GND V13 IO162NDB4V1 V14 IO160NDB4V0 V15 IO160PDB4V0 V16 IO158NDB4V0 V17 IO158PDB4V0 ...

Page 192

... Package Pin Assignments 484-Pin FBGA Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner visio ...

Page 193

FBGA Pin Number A3P600L Function A1 GND A2 GND A3 VCCIB0 IO09RSB0 A7 IO15RSB0 A10 IO22RSB0 A11 IO23RSB0 A12 IO29RSB0 A13 IO35RSB0 A14 NC A15 NC A16 IO46RSB0 A17 IO48RSB0 ...

Page 194

Package Pin Assignments 484-Pin FBGA Pin Number A3P600L Function C21 NC C22 VCCIB1 GND D5 GAA0/IO00RSB0 D6 GAA1/IO01RSB0 D7 GAB0/IO02RSB0 D8 IO11RSB0 D9 IO16RSB0 D10 IO18RSB0 D11 IO28RSB0 D12 IO34RSB0 D13 IO37RSB0 D14 ...

Page 195

FBGA Pin Number A3P600L Function H19 IO66PDB1 H20 VCC H21 NC H22 IO166NDB3 J5 IO168NPB3 J6 IO167PPB3 J7 IO169PDB3 J8 VCCIB3 J9 GND J10 VCC J11 VCC J12 VCC J13 VCC ...

Page 196

Package Pin Assignments 484-Pin FBGA Pin Number A3P600L Function N17 IO80NPB1 N18 IO74NPB1 N19 IO72NDB1 N20 NC N21 IO79NPB1 N22 IO153PDB3 P3 IO153NDB3 P4 IO159NDB3 P5 IO156NPB3 P6 IO151PPB3 P7 IO158PPB3 P8 VCCIB3 P9 GND P10 ...

Page 197

FBGA Pin Number A3P600L Function V15 IO96RSB2 V16 GDB2/IO90RSB2 V17 TDI V18 GNDQ V19 TDO V20 GND V21 NC V22 IO148PDB3 GND W5 IO137RSB2 W6 FF/GEB2/IO142RSB 2 W7 IO134RSB2 W8 IO125RSB2 W9 ...

Page 198

... IO118RSB2 AB19 NC AB20 VCCIB2 AB21 GND AB22 GND B1 GND B2 VCCIB3 IO06RSB0 B5 IO08RSB0 B6 IO12RSB0 R e visio n 9 484-Pin FBGA Pin Number A3P1000L Function B7 IO15RSB0 B8 IO19RSB0 B9 IO24RSB0 B10 IO31RSB0 B11 IO39RSB0 B12 IO48RSB0 B13 IO54RSB0 B14 IO58RSB0 B15 IO63RSB0 B16 IO66RSB0 B17 IO68RSB0 ...

Page 199

... VMV0 F18 IO78NDB1 F19 IO81NDB1 F20 IO82PPB1 F21 NC F22 IO84NDB1 G1 IO214NDB3 G2 IO214PDB3 IO222NDB3 ProASIC3L Low Power Flash FPGAs 484-Pin FBGA Pin Number A3P1000L Function G5 IO222PDB3 G6 GAC2/IO223PDB3 G7 IO223NDB3 G8 GNDQ G9 IO23RSB0 G10 IO29RSB0 G11 IO33RSB0 G12 IO46RSB0 G13 IO52RSB0 G14 IO60RSB0 G15 GNDQ ...

Page 200

... L15 GCC0/IO91NPB1 L16 GCB1/IO92PPB1 L17 GCA0/IO93NPB1 L18 IO96NPB1 L19 GCB0/IO92NPB1 L20 IO97PDB1 L21 IO97NDB1 L22 IO99NPB1 IO200NDB3 R e visio n 9 484-Pin FBGA Pin Number A3P1000L Function M3 IO206NDB3 M4 GFA2/IO206PDB3 M5 GFA1/IO207PDB3 M6 VCCPLF M7 IO205NDB3 M8 GFB2/IO205PDB3 M9 VCC M10 GND M11 GND M12 GND M13 GND ...

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