A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 100

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3L DC and Switching Characteristics
Table 2-148 • Minimum and Maximum DC Input and Output Levels
Figure 2-18 • AC Loading
Table 2-149 • AC Waveforms, Measuring Points, and Capacitive Loads
2- 86
HSTL Class II
Drive
Strength
15 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Output drive strength is below JEDEC specification.
Input Low (V)
VREF – 0.1
*
Measuring point = V
3
HSTL Class II
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull
output buffer.
Min.
–0.3 VREF – 0.1 VREF + 0.1 1.575
V
Input High (V)
trip
VREF + 0.1
VIL
. See
Max.
V
Table 2-15 on page 2-12
Min.
V
Measuring
Point* (V)
VIH
Test Point
0.75
Max.
HSTL
Class II
V
for a complete table of trip points.
R e visio n 9
Max.
VOL
VREF (typ.) (V)
0.4
V
V
TT
25
20 pF
0.75
VCCI – 0.4 15 15
VOH
Min.
V
mA mA
I
VTT (typ.) (V)
OL
I
OH
0.75
Max.
mA
I
OSL
66
1
Max.
I
mA
OSH
55
C
LOAD
1
20
µA
I
10
(pF)
IL
2
µA
I
10
IH
2