A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 105

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-160 • Minimum and Maximum DC Input and Output Levels
Figure 2-21 • AC Loading
Table 2-161 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-162 • SSTL3 Class I – Applies to 1.5 V DC Core Voltage
Table 2-163 • SSTL3 Class I – Applies to 1.2 V DC Core Voltage
SSTL3 Class I
Drive
Strength
14 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.2
*
Speed
Grade
Std.
–1
Note:
Speed
Grade
Std.
–1
Note:
Measuring point = Vtrip. See
For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Applicable to Pro I/O Banks
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V VREF = 1.5 V
Applicable to Pro I/O Banks
t
t
DOUT
0.59
0.50
DOUT
0.77
0.66
Min.
–0.3 VREF – 0.2 VREF + 0.2
V
Input High (V)
VREF + 0.2
VIL
2.08
1.77
2.08
1.77
t
t
DP
DP
Max.
V
Table 2-15 on page 2-12
0.04
0.03
0.05
0.04
t
t
DIN
DIN
Min.
Test Point
1.81
1.54
1.81
1.54
V
Measuring
t
t
Point* (V)
PY
PY
VIH
1.5
J
J
= 70°C, Worst-Case VCC = 1.425 V,
= 70°C, Worst-Case VCC = 1.14 V,
t
t
Max.
0.38
0.33
0.50
0.43
EOUT
EOUT
3.6
V
SSTL3
Class I
for a complete table of trip points.
25
R e v i s i o n 9
VREF (typ.) (V)
Max.
VOL
2.11
1.80
2.11
1.80
0.7
t
t
V
ZL
ZL
V
TT
1.5
50
30 pF
VCCI – 1.1 14 14
1.65
1.41
1.65
1.41
t
t
ZH
ZH
VOH
Min.
V
Table 2-6 on page 2-7
Table 2-6 on page 2-7
t
t
LZ
LZ
mA mA
VTT (typ.) (V)
I
OL
ProASIC3L Low Power Flash FPGAs
1.485
t
t
I
HZ
HZ
OH
Max.
mA
1.80
1.80
I
t
2.11
t
2.11
OSL
ZLS
ZLS
51
1
for derating values.
for derating values.
t
1.65
1.41
t
1.65
1.41
Max.
mA
I
ZHS
ZHS
C
OSH
54
LOAD
1
30
µA
I
10 10
(pF)
Units
Units
IL
2
ns
ns
ns
ns
µA
2- 91
I
IH
2