A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 11

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1-3 • ProASIC3L Flash*Freeze Mode
Figure 1-4 • VersaTile Configurations
X1
X2
X3
LUT-3 Equivalent
LUT-3
Flash*Freeze Technology
The ProASIC3L devices offer Actel's proven Flash*Freeze technology, which enables designers to
instantaneously shut off dynamic power consumption while retaining all SRAM and register information.
Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by
activating the Flash*Freeze (FF) pin while all power supplies are kept at their original values. In addition,
I/Os and global I/Os can still be driven and can be toggling without impact on power consumption; clocks
can still be driven or can be toggling without impact on power consumption; and the device retains all
core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can
be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is
consumed by the I/O banks, clocks, JTAG pins, or PLL. Flash*Freeze technology allows the user to
switch to active mode on demand, thus simplifying the power management of the device.
The FF pin (active low) can be routed internally to the core to allow the user's logic to decide when it is
safe to transition to this mode. It is also possible to use the FF pin as a regular I/O if Flash*Freeze mode
usage is not planned, which is advantageous because of the inherent low-power static and dynamic
capabilities of the ProASIC3L device. Refer to
Flash*Freeze mode.
VersaTiles
The ProASIC3L core consists of VersaTiles, which have been enhanced beyond the ProASIC
tiles. The ProASIC3L VersaTile supports the following:
Refer to
•
•
•
•
Y
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Figure 1-4
Mode Control
Flash*Freeze
for VersaTile configurations.
D-Flip-Flop with Clear or Set
Data
CLK
CLR
D-FF
R e v i s i o n 9
Flash*Freeze Pin
Y
Actel ProASIC3L
Figure 1-3
FPGA
Enable D-Flip-Flop with Clear or Set
Enable
for an illustration of entering/exiting
Data
ProASIC3L Low Power Flash FPGAs
CLK
CLR
D-FF
Y
PLUS®
core
1 -5