A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 13

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The CCC block has these key features:
Additional CCC specifications:
Global Clocking
ProASIC3L devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The ProASIC3L family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,
1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). ProASIC3L FPGAs support different I/O standards,
including single-ended, differential, and voltage-referenced (ProASIC3EL only). The I/Os are organized
into banks, with two, four, or eight (ProASIC3EL only) banks per device. The configuration of these banks
determines the I/O standards supported. For ProASIC3EL, each I/O bank is subdivided into V
minibanks, which are used by voltage-referenced I/Os. V
in a given minibank share a common V
configured as a V
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
ProASIC3L banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up
to 20 loads.
Wide Range I/O Support
Actel ProASIC3L devices support JEDEC-defined wide range I/O operation. ProASIC3L devices support
both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of
2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to
1.575 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the
flexibility to easily run custom voltage applications.
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Wide input frequency range (f
Output frequency range (f
2 programmable delay types for clock skew minimization
Clock frequency synthesis
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration.
Output duty cycle = 50% ± 1.5% or better
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used
Maximum acquisition time is 300 µs
Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
f
Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).
OUT_CCC
REF
pin, the remaining I/Os in that minibank will be able to use that reference voltage.
OUT_CCC
IN_CCC
) = 0.75 MHz up to 250 MHz
REF
) = 1.5 MHz up to 250 MHz
R e v i s i o n 9
line. Therefore, if any I/O in a given V
REF
minibanks contain 8 to 18 I/Os. All the I/Os
ProASIC3L Low Power Flash FPGAs
REF
minibank is
REF
1 -7