A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 141
A3P1000L-PQG208
Manufacturer Part Number
A3P1000L-PQG208
Description
FPGA - Field Programmable Gate Array 1M SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P1000L-PQG208
Processor Series
A3P1000
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
154
Data Ram Size
147456
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
1 M
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P1000L-PQG208
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Table 2-207 • ProASIC3LP CCC/PLL Specification
Note:
Figure 2-40 • Peak-to-Peak Jitter Definition
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Serial Clock (SCLK) for Dynamic PLL
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay Block
Input Period Jitter
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.
4. Maximum value obtained for a –1 speed grade device in worst-case commercial conditions. For specific junction
Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
temperature and voltage supply levels, refer to
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
J
= 25°C, VCC = 1.5 V
Peak-to-peak jitter measurements are defined by T
Output Signal
CCC/PLL Operating at 1.5 V
1, 2
4
CCC_OUT
IN_CCC
1, 2
1, 2
OUT_CCC
Table 2-6 on page 2-7
1, 2
T
period_max
peak-to-peak
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
Table 2-6 on page 2-7
R e v i s i o n 9
= T
for derating values.
period_max
T
period_min
Max Peak-to-Peak Period Jitter
1 Global
Network
0.50%
1.00%
1.75%
2.50%
0.025
Used
Min.
0.75
48.5
0.6
for deratings.
1.5
– T
period_min
ProASIC3L Low Power Flash FPGAs
Typ.
160
2.2
.
Networks
3 Global
0.70%
1.20%
5.60%
Used
Max.
2.00
5.56
5.56
350
350
110
300
51.5
1.5
6.0
1.6
0.8
32
Units
MHz
MHz
ms
ns
ns
%
ps
ns
µs
ns
ns
ns
2- 127
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