A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 221

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision
Revision 4 (cont’d)
Revision 3 (Apr 2008)
Product Brief v1.0
Packaging v1.1
Revision 2 (Apr 2008)
Product Brief rev. 1
Revision 1 (Feb 2008) The
DC
Characteristics
Advance v0.2
and
Switching
The
The value of C
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software
Settings
Default I/O Software Settings
The last section of
Power Consumption in ProASIC3L Devices at 1.2 V VCC
table:
Consumption in ProASIC3L Devices at 1.5 V
for device-specific dynamic power for P
Table 2-17 • Different Components Contributing to Dynamic Power Consumption
in ProASIC3L Devices at 1.2 V
parameters P
Contributing to the Static Power Consumption in ProASIC3L
The
calculation of P
Footnote 1
Table 2-42 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (Typ) for
Schmitt Mode Input Buffers
LVCMOS.
The
The product brief was divided into two sections and given a version number,
starting at v1.0. The first section of the document includes features, benefits,
ordering information, and temperature and speed grade offerings. The second
section is a device family overview.
Reference to M1A3P250L was removed from
Product
Information"
regarding M1A3P250L was removed from the
Table 2-198 • A3P250L Global Resource – Applies to 1.5 V DC Core
Table 2-200 • A3P600L Global Resource – Applies to 1.5 V DC Core
Table 2-202 • A3P1000L Global Resource – Applies to 1.5 V DC Core
and
Voltage
The worst-case commercial conditions were added to
FlashROM Access Time– Applies to 1.2 V DC Core
Table 2-17 • Different Components Contributing to Dynamic Power Consumption
in ProASIC3L Devices at 1.2 V VCC
and add parameters P
"Total Static Power Consumption—P
"1.2 V LVCMOS (JESD8-12A)" section
"324-Pin FBGA"
"PLL Behavior at Brownout Condition" section
Table 2-204 • A3PE3000L Global Resource – Applies to 1.5 V DC Core
Table 2-18 • Different Components Contributing to Dynamic Power
were updated with values for t
1
Family, the
through
was updated to include information about P
section, and the
DC6
STAT
LOAD
and P
Table 2-16 • Summary of I/O Output Buffer Power (per pin) –
, including P
Table 2-17 • Different Components Contributing to Dynamic
package diagram was replaced.
for single-ended 3.3 V PCI was changed to 10 from 5 in
DC1
"I/Os Per Package
DC7
through P
was updated to include the hysteresis value for 1.2 V
"Temperature Grade Offerings"
were added to
1
.
DC6
VCC. The definition of P
R e v i s i o n 9
Changes
and P
DC5
was updated to revise the value for P
RCKL
to the table.
STAT
DC7
, t
1
is new.
AC9
"
RCKH
VCC. The table numbers referenced
Table 2-19 • Different Components
.
" section
"I/Os Per Package
table, the
Table 1 • ProASIC3 Low-Power
and P
, and t
is new.
Voltage.
AC13
was updated to revise the
Table 2-215 • Embedded
AC10
RCKSW
DC5
"ProASIC3L Ordering
was made into a new
.
Devices.
table. The table note
ProASIC3L Low Power Flash FPGAs
were changed in
.
was updated and
1
"
table.
Voltage,
Voltage,
Voltage,
AC14
I, II, III,
through
2-122
2-125
2-143
Page
2-11
2-12
2-13
2-15
2-16
2-37
2-71
3-29
2-13
N/A
2-4
IV
–
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