A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 27

• Manufacturer Part Number: A3P1000L-PQG208
• Description: FPGA - Field Programmable Gate Array 1M SYSTEM GATES
• Manufacturer: Actel

Specifications of A3P1000L-PQG208

• Processor Series: A3P1000
• Core: IP Core
• Maximum Operating Frequency: 781.25 MHz
• Number Of Programmable I/os: 154
• Data Ram Size: 147456
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 1 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-17 • Different Components Contributing to Dynamic Power Consumption in ProASIC3L Devices at
Parameter
P
P
P
P
P
P
P
P
P
P
P
P
P
*
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet
calculator or SmartPower tool in Libero IDE.
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
Clock contribution of a VersaTile used as a sequential
module
First contribution of a VersaTile used as a sequential
module
Second contribution of a VersaTile used as a sequential
module
Contribution of a VersaTile used as a combinatorial
Module
Average contribution of a routing net
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
Average contribution of a RAM block during a read
operation
Average contribution of a RAM block during a write
operation
Dynamic contribution for PLL
Power Consumption of Various Internal Resources
1.2 V VCC
Definition
R e v i s i o n 9
A3PE3000L A3P1000L A3P600L A3P250L
Device Specific Dynamic Power (µW/MHz)
12.61
2.66
0.56
See
See
Table 2-14 on page 2-11
Table 2-11 on page
Table 2-13 on page
Table 2-16 on page
ProASIC3L Low Power Flash FPGAs
9.28
1.59
25.00
30.00
0.07
0.05
0.19
0.45
1.74
0.11
0.52
8.19
1.19
2-9. through
2-10.
2-12.
through
7.07
1.01
2- 13