A3P1000L-PQG208 Actel, A3P1000L-PQG208 Datasheet - Page 37

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A3P1000L-PQG208

Manufacturer Part Number
A3P1000L-PQG208
Description
FPGA - Field Programmable Gate Array 1M SYSTEM GATES
Manufacturer
Actel
Datasheet

Specifications of A3P1000L-PQG208

Processor Series
A3P1000
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
154
Data Ram Size
147456
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
1 M
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3P1000L-PQG208
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-23 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
3.3 V LVCMOS
Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
3.3 V PCI-X
Notes:
1. Currents are measured at 85°C junction temperature.
2. Output slew rate can be extracted using the IBIS Models
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification.
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
3.3 V LVCMOS
Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
3.3 V PCI
3.3 V PCI-X
Notes:
1. Currents are measured at 85°C junction temperature.
2. Output slew rate can be extracted using the IBIS Models.
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification.
Industrial Conditions—Software Default Settings
Applicable to Advanced I/O Banks
Industrial Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks
Strength
Strength
12 mA
12 mA
12 mA
12 mA
Drive
12 mA
12 mA
Drive
8 mA
4 mA
2 mA
2 mA
Any
Any
3
3
Slew
Rate
High –0.3
Slew
Rate
High
High –0.3
High –0.3
High –0.3 0.35 * VCCI 0.65 * VCCI
High –0.3 0.35 * VCCI 0.65 * VCCI 1.575
High –0.3 0.35 * VCCI 0.65 * VCCI
High
High
High
High
High
Min.
Min.
–0.3
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3
–0.3
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
V
V
VIL
VIL
Max.
0.8
0.7
Max.
0.8
V
0.7
0.8
0.8
V
Per PCI-X specifications
Per PCI-X specifications
Per PCI specifications
Per PCI specifications
R e v i s i o n 9
Min.
1.7
Min.
V
2
2
1.7
V
2
2
VIH
VIH
Max.
1.26
2.7
1.9
3.6
3.6
1.575
Max.
V
1.26
2.7
1.9
3.6
3.6
V
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI
0.25 * VCCI 0.75 * VCCI 12
0.25 * VCCI 0.75 * VCCI
Max.
VOL
0.45
0.4
0.7
0.2
V
Max.
VOL
0.45
0.4
0.2
0.7
ProASIC3L Low Power Flash FPGAs
V
VCCI – 0.45
VCCI – 0.2
VCCI – 0.45 12
VCCI – 0.2
VOH
Min.
2.4
1.7
VOH
V
Min.
2.4
1.7
V
I
mA
0.1
OL
I
12
12
mA mA
2
OL
8
4
0.1 0.1
12
12
2
1
1
I
I
mA
OH
0.1
OH
12
12
12
12
12
12
2
2- 23
2
8
4
1
1

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