LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 144
LFXP3C-3TN100I
Manufacturer Part Number
LFXP3C-3TN100I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
Manufacturer
Lattice
Specifications of LFXP3C-3TN100I
Number Of Programmable I/os
62
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-100
Package
100TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
62
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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age that is used by the DQS transition detector circuit. This voltage divider is only present on V
able on V
Lattice technical note number TN1050, LatticeECP/EC DDR Usage Guide.
Mixed Voltage Support in a Bank
The LatticeECP/EC and LatticeXP sysIO buffer is connected to three parallel ratioed input buffers. These three par-
allel buffers are connected to V
as fixed thresholds for 3.3V (V
assigned on a pin-by-pin basis, rather than tracking it with V
ratioed inputs and is independent of the bank V
have 1.2V and 3.3V ratioed input buffers with fixed thresholds, as well as 2.5V ratioed inputs with tracking thresh-
olds.
Prior to device configuration, the ratioed input thresholds always track the bank V
after configuration. Output standards within a bank are always set by V
that the user can mix in the same bank.
Table 8-2. Mixed Voltage Support
V
1.2V
1.5V
1.8V
2.5V
3.3V
CCIO
REF2.
1.2V
Yes
Yes
Yes
Yes
Yes
For more information on the DQS transition detect logic and its implementation please refer to
1.5V
Yes
Input sysIO Standards
CCAUX
CCIO,
1.8V
Yes
) and 1.2V (V
V
CCAUX
2.5V
Yes
Yes
Yes
Yes
Yes
and to V
CCIO
CC
) inputs. This allows the input threshold for ratioed buffers to be
voltage. For example, if the bank V
CC
3.3V
Yes
Yes
Yes
Yes
Yes
8-4
giving support for thresholds that track with V
CCIO.
This option is available for all 1.2V, 2.5V and 3.3V
1.2V
Yes
CCIO.
1.5V
Yes
LatticeECP/EC and LatticeXP
Output sysIO Standards
Table 8-2 shows the sysIO standards
CCIO,
1.8V
CCIO
Yes
this option only takes effect
sysIO Usage Guide
is 1.8V, it is possible to
REF1
2.5V
Yes
it is not avail-
CCIO
3.3V
as well
Yes
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