LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 202
LFXP3C-3TN100I
Manufacturer Part Number
LFXP3C-3TN100I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
Manufacturer
Lattice
Specifications of LFXP3C-3TN100I
Number Of Programmable I/os
62
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-100
Package
100TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
62
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Dual Clock First In First Out (FIFO_DC) Memory: The FIFO_DC or the dual clock FIFO is also an emulated
FIFO. Again the address logic and the flag logic is implemented in the FPGA fabric around the RAM.
The ports available on the FIFO_DC are:
• Reset
• RPReset
• WrClock
• RdClock
• WrEn
• RdEn
• Data
• Q
• Full Flag
• Almost Full Flag
• Empty Flag
• Almost Empty Flag
FIFO_DC Flags: FIFO_DC, as an emulated FIFO, required the flags to be implemented in the FPGA logic around
the block RAM. Because of the two clocks, the flags are required to change clock domains from read clock to write
clock and vice versa. This adds latency to the flags either during assertion or during de-assertion. The latency can
be avoided only in one of the cases (either assertion or de-assertion).
In the current emulated FIFO, there is no latency during assertion of these flags. Thus, when these flag go true,
there is no latency. However this causes the latency during the de-assertion.
Let us assume that we start to write into the FIFO_DC to fill it. The write operation is controlled by WrClock and
WrEn, however it takes extra RdClock cycles for de-assertion of Empty and Almost Empty flags.
On the other hand, de-assertion of Full and Almost Full result in reading out the data from the FIFO_DC. It takes
extra WrClock cycles after reading the data for these flags to come out.
With this in mind, let us look at the FIFO_DC without output register waveforms. Figure 9-42 shows the operation of
the FIFO_DC when it is empty and the data starts to get written into it.
9-37
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