CY3280-MBR Cypress Semiconductor Corp, CY3280-MBR Datasheet - Page 10

• Manufacturer Part Number: CY3280-MBR
• Description: BOARD EVAL CAPSENSE EXPRESS
• Manufacturer: Cypress Semiconductor Corp
• Series: CapSense® Express™ SmartSense™r

Specifications of CY3280-MBR

• Design Resources: CY3280-MBR Schematic CY3280-MBR Bill of Materials CY3280-MBR Gerber Files CY3280-MBR Board Layout
• Sensor Type: Touch, Capacitive
• Sensing Range: 4 Buttons/Keys
• Voltage - Supply: 3V
• Embedded: No
• Utilized Ic / Part: CY8CMBR2044
• Operating Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Current: 2.88 A
• Silicon Core Number: CY8CMBR2044
• Silicon Family Name: PSoC
• Kit Contents: 2x AAA Batteries, Axial Capacitors 10pF, 22pF, 33pF, 68pF, Quick Start Guide
• Rohs Compliant: Yes
• For Use With/related Products: CY8CMBR2044
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Sensitivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-3083

Kit Operation
2.4
2.4.1
2.4.2
10
Connector Details
SmartSense Evaluation Header (Connector J5)
Various signals are connected to the J5 connector, as shown in the following table. For more infor-
mation on each signal, see the schematics of the CY3280-MBR kit.
VDD and GND are connected to pin #1 and pin #2 on this connector such that external power supply
can be connected to kit, if required. This power supply is not gated through CapSense based power
buttons; therefore, the same voltage applied on the connector reaches the CapSense controller.
When the kit is powered though J5 connector, only CapSense controller is powered, LEDs and other
part of kit do not function.
It is not recommended to power the kit through J5 connector and one of the gated power sources.
Pin #3 of the J5 connector is connected to reset pin (XRES) of the CapSense controller; providing
logic high signal to this pin resets the CapSense controller.
The remaining two pins (pin #4 and pin #5) are connected to CapSense sensors BTN1 and BTN2,
respectively. This is done to provide an option to increase the capacitance of the sensor and evalu-
ate the SmartSense based auto tuning feature of CY8CMBR2044.
Connector J5 (SmartSense Evaluation Header)
Expansion Connector One (Connector J1)
All the GPO signals are connected to J1 connector, allowing the output signals of CapSense to be
interfaced with host controllers. This is a good option to build a mock design for testing purposes.
All hardware strapping inputs of CY8CMBR2044, except ARST, are connected to connector J1.
These signals can be used to measure the value of the strapping input resistor configured.
One end of the ScanRate/Sleep resistor is connected to pin #1 of J1. When the sleep mode is in
enabled state by making SW2 in Sleep On, the CapSense controller can be made to work in deep
sleep mode by providing recommended logic signal on the pin 1 of J1 connector. Refer the
CY8CMBR2044 data sheet
consumption of CapSense controller to 100 nA.
Connector J1 (Expansion Connector -1)
J5 - 1
J5 - 2
J5 - 3
J5 - 4
J5 - 5
J1 - 1
J1 - 2
J1 - 3
J1 - 4
J1 - 5
J1 - 6
J1 - 7
J1 - 8
J1 - 9
J1 - 10
CY3280-MBR CapSense Express with SmartSense Auto-Tuning Kit Guide, Doc. # 001-64772 Rev. **
VDD (external only to CapSense controller)
GND
XRES
CS1 (BTN1)
CS2 (BTN2)
SLEEP_CNT (control input of ScanRate/Sleep)
XRES
DELAY
TOGGLE/FSS
GND
GND
GPO 0
GPO 1
GPO 2
GPO 3
for details on how to activate deep sleep mode and reduce the current