MT9V011P11STC:B Aptina LLC, MT9V011P11STC:B Datasheet

SENSOR IMAGE VGA COLOR CMOS PLCC

MT9V011P11STC:B

Manufacturer Part Number
MT9V011P11STC:B
Description
SENSOR IMAGE VGA COLOR CMOS PLCC
Manufacturer
Aptina LLC
Series
DigitalClarity®, Micron®r
Type
CMOS Imagingr

Specifications of MT9V011P11STC:B

Pixel Size
5.6µm x 5.6µm
Active Pixel Array
640H x 480V
Frames Per Second
30
Voltage - Supply
2.8V
Package / Case
28-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1315

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT9V011P11STC:B
Manufacturer:
RENESAS
Quantity:
1 001
Part Number:
MT9V011P11STC:B
Manufacturer:
MICRON
Quantity:
20 000
1/4-Inch VGA CMOS Digital Image Sensor
Part Number: MT9V011P11STC:B
For the latest data sheet revision, please refer to Micron’s Web site: www.micron.com/imaging
Features
• DigitalClarity™ CMOS Imaging Technology
• Ultra low-power, low cost CMOS image sensor
• Superior low-light performance
• Simple two-wire serial interface
• Auto black level calibration
• Window Size: VGA, programmable to any smaller
• Programmable Controls: Gain, frame rate, left-right
Applications
• Cellular phones
• PDAs
• PC Cameras
• Toys and other battery-powered products
General Description
The Micron® Imaging MT9V011 is a 1/4-inch VGA-for-
mat CMOS active-pixel digital image sensor. The active
imaging pixel array is 649H x 489V. It incorporates
sophisticated camera functions on-chip such as win-
dowing, column and row mirroring. It is programma-
ble through a simple two-wire serial bus interface and
has very low power consumption.
The MT9V011 features DigitalClarity—Micron’s break-
through low-noise CMOS imaging technology that
achieves CCD image quality (based on signal-to-noise
ratio and low-light sensitivity) while maintaining the
inherent size, cost and integration advantages of
CMOS.
PDF: 817d5189/Source: 817d5173
MT9V011_C82S_1_PLCC.fm - Rev. B 1/05 EN
Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron
format (QVGA, CIF)
and top-bottom image reversal, window size and
panning
to meet Micron’s production data sheet specifications.
MT9V011 - 1/4-Inch VGA Digital Image Sensor
1
Table 1:
The sensor can be operated in its default mode or pro-
grammed by the user for frame size, exposure, gain set-
ting, and other parameters. The default mode outputs
a VGA-size image at 30 frames per second (fps). An on-
chip analog-to-digital converter (ADC) provides 10 bits
per pixel. FRAME_VALID and LINE_VALID signals are
output on dedicated pins, along with a pixel clock
which is synchronous with valid data.
Optical Format
Active Imager Size
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Maximum Data Rate/
Master Clock
ADC Resolution
Responsivity
Dynamic Range
SNR
Supply Voltage
Power Consumption
Operating Temperature
Packaging
Frame
Rate
MAX
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Parameter
VGA (640 x 480)
CIF (352 x 288)
QVGA (320 x 240)
Key Performance Parameters
©2004 Micron Technology, Inc. All rights reserved.
1/4-inch (4:3)
3.58mm(H) x 2.69mm(V),
4.48mm Diagonal
640H x 480V
5.6um x 5.6um
RGB Bayer Pattern
Electronic Rolling Shutter
(ERS)
13.5 MPS/27 MHz
30 fps at 27 MHz
Programmable up to 60 fps
Programmable up to 90 fps
10-bit, on-chip
1.9 V/lux-sec (550nm)
60dB
45dB
2.8V
70mW at 2.8V,
27 MHz, 30 fps
-20°C to +60°C
28-Pin PLCC
±
Typical Value
0.25V
Preliminary
Features

Related parts for MT9V011P11STC:B

MT9V011P11STC:B Summary of contents

Page 1

... VGA CMOS Digital Image Sensor Part Number: MT9V011P11STC:B For the latest data sheet revision, please refer to Micron’s Web site: www.micron.com/imaging Features • DigitalClarity™ CMOS Imaging Technology • Ultra low-power, low cost CMOS image sensor • Superior low-light performance • ...

Page 2

Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

List of Figures Figure 1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

List of Tables Table 1: Key Performance Parameters ...

Page 5

Figure 1: Block Diagram Active-Pixel Sensor (APS) Array 668H x 496V Analog Processing Figure 2: Typical Configuration (Connection) Two-wire serial bus Note: 1.5KΩ resistor value is recommended, but may be higher for slower two-wire speed. PDF: 817d5189/Source: 817d5173 MT9V011_C82S_2_PLCC.fm - ...

Page 6

Figure 3: 28-Pin PLCC Package Pinout Diagram V A VAAPIX SCAN_EN RESET# STANDBY Table 2: Pin Description Pin Number Name Type 12 V Power AA 14 VAAPIX Power 1 V Power Ground GND 11 Ground ...

Page 7

Table 2: Pin Description (continued) Pin Number Name Type Output OUT Output OUT Output OUT Output OUT Output OUT Output OUT 6 ...

Page 8

Pixel Data Format Pixel Array Structure The MT9V011’s pixel array is 668 columns by 496 rows. The first 18 columns and the first 6 rows of pixels are optically black and can be used to monitor the black level. The ...

Page 9

Figure 6: Spatial Illustration of Image Readout 0,0 0,1 0 1,0 1,1 1 .....................................P m-1,0 m-1 .....................................P m,0 m ..................................... ..................................... ...

Page 10

Frame Timing Formulas Table 3: Frame Time Parameter Name A Active Data Time P Frame Start/End Blanking 6 x (Reg0x0A + 2) Q Horizontal Blanking A+Q Row Time V Vertical Blanking Frame Valid Time rows ...

Page 11

Serial Bus Description Registers are written to and read from the MT9V011 through the two-wire serial inter- face bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial ...

Page 12

Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of seven bits of address and 1 ...

Page 13

Two-wire Serial Interface Sample Read and Write Sequences 16-Bit Write Sequence A typical write sequence for writing 16 bits to a register is shown in Figure 9. A start bit given by the master, followed by the write address, starts ...

Page 14

Eight-Bit Write Sequence To be able to write one byte at a time to the register a special register address is added. The 8-bit write is done by first writing the upper eight bits to the desired register and then ...

Page 15

Registers Register Map Table 6: Register Map Register # (Hex) Description 0x00/0xFF Chip Version 0x01 Row Start 0x02 Column Start 0x03 Window Height 0x04 Window Width 0x05 Horizontal Blanking 0x06 Vertical Blanking 0x07 Output Control 0x09 Shutter Width 0x0A Pixel ...

Page 16

Table 6: Register Map (continued) Register # (Hex) Description 0x5E Reserved 0x5F Reserved 0x60 Reserved 0x61 Reserved 0x62 Reserved 0x63 Reserved 0x64 Reserved 0x65 Reserved 0xF1 Chip Enable 0xF7 Reserved 0xF8 Reserved 0xF9 Reserved 0xFA Reserved 0xFB Reserved 0xFC Reserved ...

Page 17

Register Descriptions Table 7: Register Description Register Bit Chip Version 0x00 / 0xFF 0-15 This register is read-only and gives the chip identification number: 0x8243. Window Control These registers control the size of the window. 0x01 0-8 First row to ...

Page 18

Table 7: Register Description (continued) Register Bit Pixel Integration Control These registers (along with the Window Size and Blanking registers) control the integration time for the pixels. 0x09 0-11 Number of rows of integration, default = 0x01FC (508). 0x0C 0-9 ...

Page 19

Table 7: Register Description (continued) Register Bit To preserve a right-reading image and the correct color order, all four of these bits should be set to “1” to invert the image readout starting 1 column later. 0 ...

Page 20

Feature Description Window Control Reg0x01 Row Start, Reg0x02 Column Start, Reg0x03 Window Height (row size), and Reg0x04 Window Width (column size) These registers control the size and starting coordinates of the window. By changing these registers, any image format smaller ...

Page 21

when Reg0x07[ this expression the row time term corresponds to the number of rows integrated. The overhead time is the time between the READ cycle and the RESET cycle, and the final term is ...

Page 22

Figure 13: Readout of 4 Pixels in Normal and Zoom 2x Output Mode LINE_VALID Normal readout D -D OUT9 PIXCLK LINE_VALID Zoom 2X readout D -D OUT9 PIXCLK True Decimation mode Reg0x1E Digital Zoom/True decimation True decimation mode is intended ...

Page 23

Figure 16: Readout of 6 Rows in Normal and Row Mirror Output Mode FRAME_VALID Normal readout DOUT9-DOUT0 Reverse readout DOUT9-DOUT0 Column and Row Skip By setting bit 3 of Reg0x20 only half of the columns set will be read out, ...

Page 24

The analog gain circuitry (pre-ADC) is designed to offer signal gains from 1 to 15.875. The minimum gain of 1 (register set to 0x0020) corresponds to the lowest setting where the pixel signal is guaranteed to saturate the ADC under ...

Page 25

Electrical Specifications Table 10: DC Electrical Characteristics ( 2.8 ±0.25V Symbol Definition V Input High Voltage IH V Input Low Voltage IL I Input Leakage Current IN V Output High Voltage OH V Output ...

Page 26

Table 11: AC Electrical Characteristics ( 2.8 ±0.25V Symbol Definition f Input Clock Frequency CLKIN Clock Duty Cycle t R Input Clock Rise Time t F Input Clock Fall Time CLKIN to PIXCLK propagation ...

Page 27

Propagation Delays for PIXCLK and Data Out Signals The typical output delay, relative to the master clock edge, is 7.5 ns. Note that the data outputs change on the falling edge of the master clock, with the pixel clock rising ...

Page 28

Figure 21: Data Output Timing Diagram PIXCLK t FVSETUP FRAME_VALID LINE_VALID D (9:0) OUT PIXCLK = max. 27 MHz t FVSETUP t FVHOLD t LVSETUP t LVHOLD setup time for D DSETUP hold time ...

Page 29

Two-Wire Serial Bus Timing The two-wire serial bus operation requires certain minimum master clock cycles between transitions. These are specified in the following diagrams in master clock cycles. Figure 22: Serial Host Interface Start Condition Timing SCLK SDATA Figure 23: ...

Page 30

Figure 26: Acknowledge Signal Timing After an 8-bit Write to the Sensor SCLK SDATA Figure 27: Acknowledge Signal Timing After an 8-bit Read from the Sensor SCLK SDATA Note: After a read, the master receiver must pull down S bits. ...

Page 31

Figure 29: Image Center Offset Chip Center Note: Not to scale. PDF: 817d5189/Source: 817d5173 MT9V011_C82S_2_PLCC.fm - Rev. B 1/05 EN MT9V011 - 1/4-Inch VGA Digital Image Sensor Image Center 697.4um 14.6um Sensor Chip Micron Technology, Inc., reserves the right to ...

Page 32

Figure 30: 28-Pin PLCC Package Outline Drawing 1.70 ±0.10 2.35 ±0.15 SEATING PLANE SECTION A–A 7.62 1.27 TYP 28 1 27X 1.27 29X R0.225 7. 1.905 ±0.100 11.43 ±0.10 Note: All dimensions are in millimeters. Data Sheet Designation ...

Page 33

... Revision History Rev B, Preliminary ...........................................................................................................................................................1/05 • Updated part number: MT9V011P11STC:B • Changed chip version ID registers (R0x00/0xFF) from 0x8232 to 0x8243 in Table 6 on page 15 and Table 7 on page 17 • Table 10 on page 25: Replaced V • Table 11 on page 26: Updated definition for parameter • Updated Figure 2 on page 5, Figure 19 on page 27, Figure 20 on page 27, and Figure 21 on page 28 Rev A, Preliminary ...........................................................................................................................................................4/04 • ...

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