LAN9210-ABZJ Standard Microsystems (SMSC), LAN9210-ABZJ Datasheet - Page 116
LAN9210-ABZJ
Manufacturer Part Number
LAN9210-ABZJ
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9210-ABZJ.pdf
(147 pages)
Specifications of LAN9210-ABZJ
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Compliant
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Revision 2.7 (03-15-10)
5.5
(IN DECIMAL)
INDEX
17
18
27
29
30
31
0
1
2
3
4
5
6
The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC
via the MII_ACC and MII_DATA registers. An index must be used to access individual PHY registers.
PHY Register Indexes are shown in
Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of
PHY Registers
the PHY Basic Control Register (Reset) is set.
Table 5.8 LAN9210 PHY Control and Status Register
REGISTER NAME
Basic Control Register
Basic Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Mode Control/Status Register
Special Modes Register
Special Control/Status Indications
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
PHY CONTROL AND STATUS REGISTERS
DATASHEET
Table 5.8, "LAN9210 PHY Control and Status
116
Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Register".
SMSC LAN9210
Datasheet
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