L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet

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L-ET1011C2-CI-D

Manufacturer Part Number
L-ET1011C2-CI-D
Description
Manufacturer
LSI
Datasheet

Specifications of L-ET1011C2-CI-D

Number Of Receivers
1
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Lead Free Status / Rohs Status
Compliant

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TruePHY ™ ET1011C
Gigabit Ethernet Transceiver
Data Sheet
September 2007
10Base-T, 100Base-TX, and 1000Base-T
gigabit Ethernet transceiver:
— 0.13 µm process
— 128-pin TQFP and 84-pin MLCC:
— 68-pin MLCC:
Low power consumption:
— Typical power less than 750 mW in 1000Base-T
— Advanced power management
— ACPI compliant wake-on-LAN support
Oversampling architecture to improve signal integrity
and SNR
Optimized, extended performance echo and NEXT fil-
ters
All-digital baseline wander correction
Digital PGA control
On-chip diagnostic support
Automatic speed negotiation
Automatic speed downshift
Single supply 3.3 V or 2.5 V operation:
— On-chip regulator controllers
— 3.3 V or 2.5 V digital I/O
— 3.3 V tolerant I/O pins (MDC, MDIO, COMA,
— 1.0 V or 1.1 V core power supplies
— 1.8 V or 2.5 V for transformer center tap
JTAG
ET1011C is a pin-compatible replacement for the
ET1011 device
Commercial- and industrial-temperature versions avail-
able
mode
RESET_N, and JTAG pins)
o
o
RGMII, GMII, MII, RTBI, and TBI interfaces to
MAC or switch
RGMII and RTBI interfaces to MAC or switch
Introduction
The LSI ET1011C is a Gigabit Ethernet transceiver fabri-
cated on a single CMOS chip. Packaged in either an 128-
pin TQFP, an 84-pin MLCC, or a
68-pin MLCC, the ET1011C is built on 0.13 µm technol-
ogy for low power consumption and application in server
and desktop NIC cards. It features single power supply
operation using on-chip regulator controllers. The 10/100/
1000Base-T device is fully compliant with IEEE
802.3u, and 802.3ab standards.
The ET1011C uses an oversampling architecture to gather
more signal energy from the communication channel than
possible with traditional architectures. The additional sig-
nal energy or analog complexity transfers into the digital
domain. The result is an analog front end that delivers
robust operation, reduced cost, and lower power consump-
tion than traditional architectures.
Using oversampling has allowed for the implementation of
a fractionally spaced equalizer, which provides better
equalization and has greater immunity to timing jitter,
resulting in better signal-to-noise ratio (SNR) and thus
improved BER. In addition, advanced timing algorithms
are used to enable operation over a wider range of cabling
plants.
®
802.3,

Related parts for L-ET1011C2-CI-D

L-ET1011C2-CI-D Summary of contents

Page 1

... Introduction The LSI ET1011C is a Gigabit Ethernet transceiver fabri- cated on a single CMOS chip. Packaged in either an 128- pin TQFP, an 84-pin MLCC 68-pin MLCC, the ET1011C is built on 0.13 µm technol- ogy for low power consumption and application in server and desktop NIC cards. It features single power supply operation using on-chip regulator controllers ...

Page 2

... Package Diagram, 68-Pin MLCC ......................................83 Ordering Information .........................................................84 Table Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC........................................... 15 Table 2. Multiplexed Signals on the ET1011C .................. 20 Table 3. GMII Signal Description (1000Base-T Mode) (128-pin TQFP and 84-pin MLCC only) ........................................ 22 Table 4. RGMII Signal Description (1000Base-T Mode)........................................ 23 Table 5 ...

Page 3

... Table 38. Loopback Control Register—Address 19...........50 Table 39. Loopback Bit (0.14) and Cable Diagnostic Mode Bit (23.13) Settings for Loopback Mode...............................................50 Table 40. RX Error Counter Register—Address 20 ...........51 Table 41. Management Interface (MI) Control Register—Address 21......................................51 Table 42. PHY Configuration Register—Address 22.........52 Table 43. PHY Control Register—Address 23...................53 Table 44. Interrupt Mask Register— ...

Page 4

... Figure Contents Figure 1. ET1011C Block Diagram...................................... 5 Figure 2. Loopback Functionality ........................................ 9 Figure 3. Digital Loopback................................................... 9 Figure 4. Replica and Line Driver Analog Loopback ........ 10 Figure 5. External Cable Loopback.................................... 10 Figure 6. Pin Diagram for ET1011C in 128-Pin TQFP Package (Top View).............. 12 Figure 7. Pin Diagram for ET1011C in 84-Pin MLCC Package (Top View) .............. 13 Figure 8 ...

Page 5

... September 2007 Functional Description The LSI ET1011C is a Gigabit Ethernet transceiver that simultaneously transmits and receives on each of the four UTP pairs of category 5 cable (signal dimensions or channels and D) at 125 Msymbols/s using five-level pulse-amplitude modulation (PAM). Figure block diagram of its basic configuration. ...

Page 6

... PAM signals over the four pairs of CAT-5 cable. 100Base-TX Encoder In 100Base-TX mode, 4-bit data from the media independent interface (MII) is 4B/5B encoded to output 5-bit serial data at 125 MHz. The bit stream is sent to a scrambler, and then encoded to a three-level MLT3 sequence that is then transmitted by the PMA. 10Base-T Encoder In 10Base-T mode, the ET1011C transmits and receives Manchester-encoded data ...

Page 7

... A hybrid circuit is used to transmit and receive simultaneously on each pair. If the transmitter is not perfectly matched to the line, a signal component will be reflected back as an echo. Reflections can also occur at other connectors or cable imperfections ...

Page 8

... A hardware reset is required after powerup in order to ensure proper operation. A software reset is accomplished by setting bit 15 of the con- trol register (MII register address 0, bit 15). The configura- tion pins and the physical address configuration are not read during software reset ...

Page 9

... Selecting the MII option gives a simple loopback with minimal latency where the data is looped back directly at the media-independent interface. This loopback is currently set as the default, but it should be noted that it only exercises a small percentage of the PHY circuitry. When the all-digital option is selected, the transmitted data is looped back at the inter- face between the digital and the analog circuitry, thereby exercising a high percentage of the digital logic ...

Page 10

... For example, for wire pair A, connect a 100 Ω resistor between the leads (pins 1 and short cable plugged into the RJ45. This should also be done for wire pairs B, C, and D. Another way to accomplish this is to connect to a link partner with a short cable and power- down the link partner ...

Page 11

... COMA signal is high (asserted) or the RESET_N signal is driven low (asserted). Low-Power Energy-Detect (LPED) Mode In LPED mode, the PHY low power state but still monitors the cable (MDI interface) for energy. If energy is detected, the MDINT_N pin is asserted. During LPED mode, SYS_CLK is not available and the MII registers are not accessible ...

Page 12

... LSI 19 ET1011 ET1011C September 2007 102 VDD 101 DVSS 100 RXD[4] 99 RXD[5] 98 RXD[6] 97 RXD[7] 96 DVDDIO 95 DVSS 94 SYS_CLK 93 DVSS 92 VDD 91 MDC 90 MDIO 89 MDINT_N 88 DVDDIO 87 PRES LED_LNK/PAUSE LED_1000/SPEED_1000 81 VDD 80 DVSS 79 CTRL_1V0 78 CTRL_2V5 77 VDD_REG 76 DVSS PHYAD[0]/LED_TXRX 70 PHYAD[1]/LED_100 69 PHYAD[2] 68 PHYAD[3] 67 PHYAD[ LSI Corporation ...

Page 13

... TRST_N 12 TMS/SYS_CLK_EN_N 13 TDI/LPED_EN_N 14 TDO 15 MAC_IF_SEL[0] 16 MAC_IF_SEL[1] 17 MAC_IF_SEL[2] 18 VDD 19 AVDDL 20 AVDDH 21 Figure 7. Pin Diagram for ET1011C in 84-Pin MLCC Package (Top View) LSI Corporation LSI ET1011C AGERE SYSTEMS ET1011 EXPOSED PAD (DVSS AND AVSS) Gigabit Ethernet Transceiver 63 VDD 62 RXD[4] 61 RXD[5] 60 RXD[6] 59 RXD[7] 58 DVDDIO ...

Page 14

... TDO 8 9 MAC_IF_SEL[0] 10 MAC_IF_SEL[1] VDD 11 COMA 12 VDD 13 14 AVDDL AVDDH 15 16 CLK_IN/XTAL_1 XTAL_2 17 Figure 8. Pin Diagram for ET1011C in 68-Pin MLCC Package (Top View) 14 • LSI ET1011C EXPOSED PAD (DVSS AND AVSS) September 2007 51 DVDDIO SYS_CLK 50 49 VDD MDC 48 47 MDIO 46 MDINT_N 45 ...

Page 15

... September 2007 Pin Information (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC Name Description MAC: GMII—Gigabit Media-Independent Interface (128-Pin TQFP and 84-Pin MLCC Only) GTX_CLK GMII transmit clock ...

Page 16

... Gigabit Ethernet Transceiver Pin Information (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC Table 1. ET1011C Device Signals by Interface, 128-Pin TQFP, 84-Pin and 68-Pin MLCC (continued) Name Description MAC: TBI—Ten-Bit Interface (128-Pin TQFP and 84-Pin MLCC Only) PMA_ TX_CLK ...

Page 17

... PRES Precision resistor 1. Configuration signals are multiplexed with the LED controls. During a reset, the status of the configuration pins are latched and used to set the configura- tion and later to select the polarity to drive the LEDs. LSI Corporation Gigabit Ethernet Transceiver ...

Page 18

... Hardware powerdown CTRL_1V0 Regulator control 1.0 V CTRL_2V5 Regulator control 2 Configuration signals are multiplexed with the LED controls. During a reset, the status of the configuration pins are latched and used to set the configura- tion and later to select the polarity to drive the LEDs. 18 (continued) Pad ...

Page 19

... Reserved—do not con- nect 1. Configuration signals are multiplexed with the LED controls. During a reset, the status of the configuration pins are latched and used to set the configura- tion and later to select the polarity to drive the LEDs. 2. All AVSS and DVSS pins share a common ground pin (pad) in the center of the device. ...

Page 20

... Gigabit Ethernet Transceiver Pin Information (continued) Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC, and 68-Pin MLCC Table 2. Multiplexed Signals on the ET1011C Default 128-Pin TQFP COL CRS GTX_CLK LED_LNK LED_1000 LED_TXRX LED_100 RX_CLK RX_ER RX_DV TDI TMS TX_ER TX_EN XTAL_1 1. GMII signal. 2. TBI signal. ...

Page 21

... Management interface n Several of the pins of the MAC interface are multiplexed, but they are designed to be interchangeable so that the device can change the MAC interface once the transmission capabilities (1000Base-T, 100Base-TX, and 10Base-T) are established. The following diagram shows the various interfaces on each ET1011C and how they connect to the MAC and other support devices in a typical application ...

Page 22

... Figure 10. GMII MAC-PHY Signals Pin Description Transmit clock The MAC drives this 125 MHz clock signal that is held low during autonegotiation or when operating in modes other than 1000Base-T. Transmit error The MAC drives this signal high to indicate a transmit coding error. Transmit The MAC drives this signal high to indicate that data is available on enable the transmit data bus ...

Page 23

... RXD[3:0] 105, 106, 65, 66, 67, 107, 108 68 RX_CTL 109 69 1. Reference the GMII interface for description of the following parameters: TX_EN, TX_ER, RX_DV, RX_EN, and RX_ER. LSI Corporation Figure 11. RGMII MAC-PHY Signals Pin # Pin Description 68-Pin MLCC 63 Transmit clock The MAC drives this 125 MHz clock signal that is held low during autonegotiation ...

Page 24

... The ET1011C transmits data synchronized with RX_CLK to the MAC. bits Carrier sense The carrier sense signal (CRS) of the MAC interface is asserted by the ET1011C whenever the receive medium is nonidle. In half-duplex mode, CRS may also be asserted when the transmit medium is nonidle. The CRS may be enabled on transmit in half-duplex mode by writing to the PHY configuration register, address 22, bit 15 ...

Page 25

... Receive clock The ET1011C generates a 62.5 MHz clock to synchro- nize receive data for the odd code group. This signal is 180 degrees out of phase from PMA_RX_CLK[1]. 70, 69, 59, Receive data bits The ET1011C transmits data that is synchronized with 60, 61, 62, PMA_ RX_CLK[0] to the MAC ...

Page 26

... TXC and bits 8 nega- tive transition of TXC. 64 Transmit control The MAC transmits bit 5 and bit 10 synchronized with TXC to the ET1011C for transmission on the media- dependent (transformer) interface. The MAC trans- mits bit positive transition of TXC and bit 10 on the negative transition of TXC ...

Page 27

... ST (start of frame): The start of frame is indicated by a <01> pattern. This pattern ensures transitions from the default logic n one line state to zero and back to one. When a clause 45 start of frame <00> is received, the frame is ignored. OP (operation code): The operation code for a read transaction is <10>, while the operation code for a write transaction is n < ...

Page 28

... MDINT_N is an open-drain, active-low signal that can be wire-ORed with several other ET1011C devices. A single 2.2 kΩ pull-up resistor is recommended for this wire-OR configuration. When an interrupt occurs, the system can poll the status of the interrupt status register on each device to determine the origin of the interrupt. There are nine conditions that can be selected to generate an interrupt: ...

Page 29

... Some configuration inputs are shared with LED pins. The hardware configuration and LED pins are read on initial powerup of the ET1011C, during a hardware reset and during recovery from hardware powerdown. The logic value at the pin is sensed and latched. After RESET_N has been deasserted (raised high), the shared configuration pins become outputs that are used to drive LEDs ...

Page 30

... MAC_IF_SEL pins = 101 will set MAC interface mode select bits in register 22.2:0 = 111; alternative RGMII TXC DLL Delay bit 23 — MAC_IF_SEL pins = 110 will set MAC interface mode select bits in register 22.2:0 = 110; alternative RGMII TXC DLL Delay bit 23 — MAC_IF_SEL pins = 111 will set MAC interface mode select bits in register 22.2:0 = 111; alternative RGMII TXC DLL Delay bit 23 ...

Page 31

... The ET1011C is capable of automatically sensing the polarity of the LEDs. The device determines the active sense of the LED based upon the input that is latched during configuration. Thus, if logic 1 is read, the device will drive the pin to ground to activate the LED; otherwise, it will drive the pin to supply to activate the LED. ...

Page 32

... In 1000Base-T mode, transmit and receive occurs simultaneously at TRD[2]±. In 10Base-T and 100Base-TX modes, TRD[2]± are unused. 31 Transmit/Receive Connect this signal pair through a transformer to the 32 Differential Pair 3 media-dependent interface. In 1000Base-T mode, transmit and receive occurs simultaneously at TRD[3]±. In 10Base-T and 100Base-TX modes, TRD[3]± are unused ...

Page 33

... MHz ± 50 ppm tolerance crystal (XTAL_1). 16 Reference Crystal Input 17 Reference Connect this signal MHz ± 50 ppm tolerance Crystal Input crystal. Float this signal if an external clock is used (CLK_IN). 50 System Clock Use this signal to supply a 125 MHz clock to the MAC ...

Page 34

... Regulator Control The ET1011C has two on-chip regulator controllers. This allows the device to be powered from a single supply, either 3 2.5 V. The on-chip regulator control circuits provide output control voltages that can be used to control two external transistors and thus provide regulated 1.0 V and 2.5 V supplies. ...

Page 35

... V SS AVDDH V DD AVDDL V DD AVSS Connect 1. For 84-pin MLCC and 68-pin MLCC, all AVSS and DVSS pins share a common ground pin (exposed pad) in the center of the device. LSI Corporation 1 DVDD AVDDH VDD_REG 1.0 2.5 3.3 1.0 2.5 2.5 1.0 2.5 3 ...

Page 36

... When there is a link active, the link analysis can detect cable length, link quality, pair skew, pair swaps (MDI/MDI-X configu- ration), and polarity reversal. When there is no link, TDR can detect cable faults (open circuit, short circuit), distance to the fault, pair fault is on, cable length, pair skew, and excessive crosstalk. Table 18 summarizes the specifications of the cable diagnostic functions ...

Page 37

... Table 20. Register Type Definition Type LL Latching low. LH Latching high. R/W Read write. Register can be read or written. RO Read only. Register is read only. Writes to register are ignored. SC Self-clearing. Register is self-clearing one is written, the register will automatically clear to zero after the function is completed. LSI Corporation Description Description ...

Page 38

... This is the master enable for digital and analog loopback as defined by the standard. The exact type of loopback is determined by the loopback control register (address 19). 3. The speed selection address 0 bits 13 and 6 may be used to configure the link manually. Setting these bits has no effect unless address 0 bit 12 is clear. ...

Page 39

... This bit indicates that a remote fault has been detected. Once set, it remains set until it is cleared by reading register 1 via the management interface or by PHY reset. 4. This bit indicates that a valid link has been established. Once cleared due to link failure, this bit will remain cleared until register 1 is read via the management interface. ...

Page 40

... Gigabit Ethernet Transceiver Register Description (continued) Register Functions/Settings (continued) Table 23. PHY Identifier Register 1—Address 2 Bit Name 15:0 PHY Identifier Bits Organizationally unique identifier (OUI), bits 3:18. 3:18 Table 24. PHY Identifier Register 2—Address 3 Bit Name 15:10 PHY Identifier Bits Organizationally unique identifier (OUI), bits 19:24. ...

Page 41

... Value read from PAUSE on reset. 2. The ET1011C does not support 100Base-T4, so the default value of this register bit is zero. Note: Any write to this register prior to the completion of autonegotiation is followed by a restart of autonegotiation. Also note that this register is not updated following autonegotiation. LSI Corporation ...

Page 42

... Table 26. Autonegotiation Link Partner Ability Register—Address 5 Bit Name 15 Next page 1 = Link partner has next page ability Link partner does not have next page ability. 14 Acknowledge 1 = Link partner has received link code word Link partner has not received link code word. 13 Remote Fault 1 = Link partner has detected remote fault ...

Page 43

... Parallel link fault not detected. 3 Link Partner Next 1 = Link partner has next page capability. Page Ability 0 = Link partner does not have next page capability. 2 Next Page Capabil Local device has next page capability. ity 0 = Local device does not have next page capability. ...

Page 44

... Formatted page Unformatted page. 12 Acknowledge Complies with message Cannot comply with message. 11 Toggle 1 = Previous value of transmitted link code word was logic zero Previous value of transmitted link code word was logic one. 10:0 Message/ Next page message code or unformatted data. Unformatted Code ...

Page 45

... Capability 7:0 Reserved 1. Setting this bit has no effect unless address 9, bit 12 is set. 2. Value read from SPEED_1000 pin at reset. Note: Logically, bits 12:8 can be regarded as an extension of the technology ability field of register 4. LSI Corporation 1000Base-T Control Register Description — Gigabit Ethernet Transceiver ...

Page 46

... Note that logically, bits 11:10 may be regarded as an extension of the technology ability field of register 5. 4. These bits contain a cumulative count of the errors detected when the receiver is receiving idles and both local and remote receiver status are OK. The count is held at 255 in the event of overflow and is reset to zero by reading register 10 via the management interface or by reset. 46 ...

Page 47

... Not 1000Base-T full-duplex capable. 12 1000Base-T Half 1000Base-T half-duplex capable. duplex 0 = Not 1000Base-T half-duplex capable. 11:0 Reserved 1. Value is a result of (SPEED_1000) pin at reset. Table 34. Reserved Registers—Addresses 16—17 Bit Name 15:0 Reserved LSI Corporation Reserved Registers Description — ...

Page 48

... Diagnostics 0 = Disable diagnostics. 1:0 Reserved 1. Count symbol errors (18.13) and count false carrier events (18.14) control the type of errors that the Rx error counter (20.15:0) counts (settings are shown below). The default is to count CRC errors. Count False Count Symbol Errors Carrier Events ...

Page 49

... September 2007 Register Description (continued) Register Functions/Settings (continued) Bit 9, PHY Control Register 2, manually sets the MDI/MDI-X configuration if automatic MDIX is disabled, as indicated below. Table 36. MDI/MDI-X Configuration Automatic MDI/MDI-X MDI/MDI-X Configuration The mapping of the transmitter and receiver to pins for MDI and MDI-X configuration for 10Base-T, 100Base-TX, and 1000Base-T is shown below ...

Page 50

... Replica loopback is not available in 10Base-T. 2. This bit can be used to force link status okay during MII loopback. In MII loopback, the link status bit will not be set unless force link status is used. In all other loopback modes, the link status bit will be set when the link comes up. ...

Page 51

... Rx Error Counter 16-bit Rx error counter. Table 41. Management Interface (MI) Control Register—Address 21 Bit Name 15:3 Reserved 2 Ignore 10G Frames 1 = Management frames with ST = <00> are ignored Management frames with ST = <00> are treated as wrong frames 1 Reserved 0 Preamble Suppres preamble is ignored. sion Enable preamble is required. ...

Page 52

... If automatic speed downshift is enabled and the PHY fails to autonegotiate at 1000Base-T, the PHY will fall back to attempt connection at 100Base-TX and, subsequently, 10Base-T. This cycle will repeat. If the link is broken at any speed, the PHY will restart this process by reattempting connection at the highest possible speed (e.g., 1000Base-T). ...

Page 53

... Assert MDINT_N pin Deassert MDINT_N pin. 1. This bit is only valid when the PHY is in PHY standby mode (26. and after the IP phone detect enable bit (23.14) has been set and has self-cleared to indicate that the IP phone detection algorithm has completed. 2. Setting this bit enables the automatic IP phone detection algorithm and clears the IP phone detected bit (23.15). Diagnostics must be enabled (18.2 = 1), cable diagnostic TDR mode must be selected (23 ...

Page 54

... Interrupt disabled. 2 Link Status Change 1 = Interrupt enabled Interrupt disabled. 1 Automatic Speed 1 = Interrupt enabled. Downshift 0 = Interrupt disabled. 0 MDINT_N Enable 1 = MDINT_N enabled 0 = MDINT_N disabled. 1. MDINT_N is asserted (active-low) if MII interrupt pending = 1. 54 Interrupt Mask Register Description — September 2007 Type Default Notes — — ...

Page 55

... If the management frame preamble is suppressed (MF preamble suppression, register 0, bit 6 possible for the PHY to lose synchronization if there is a glitch at the interface. The PHY can recover if a single frame with a preamble is sent to the PHY. The MDIO sync lost interrupt can be used to detect loss of synchronization and, thus, enable recovery ...

Page 56

... Link partner advertised that direction is asymmetric. 1. This bit indicates that the PHY is in standby mode and is ready to perform IP phone detection or TDR cable diagnostics. The PHY enters standby mode when cable diagnostic TDR mode is selected (23. and the link is dropped. A software reset (0.15) or software power down (0.11) can be used to force the link to drop ...

Page 57

... Pulse Stretch two-color mode is enabled for pair LED_LINK and LED_TXRX, the signal output for LED_LINK is equal to (LED_LINK and LED_TXRX). For the case where LED_LINK and LED_TXRX are not mutually exclusive (e.g., duplex and collision), this mode can simplify the external circuitry because it ensures either LED_LINK or LED_TXRX is on, and not both at the same time ...

Page 58

... Select register set for LED_100. 13:8 LED Blink Pattern LED blink pattern clock frequency divide ratio. Frequency 7:0 LED Blink Pattern LED blink pattern. 1. The default pattern is a 512 ms blink. 58 LED Control Register 2 Description LED Control Register 3 Description September 2007 Type ...

Page 59

... The automatic algorithm searches for faults in the order of short between C and D, B and D, B and C, A and D, A and C, A and B; and faults on pair D, pair C, pair B, and pair A. If there is no fault, the result will be 0xff and should be ignored ...

Page 60

... No short between pairs C and D. 1:0 Reserved 1. For automatic TDR analysis, this returns the fault type on pair A. For single-pair TDR analysis, this returns the fault type on the pair combination under test, i.e., as specified in the TDR Tx Dim and Rx Dim (30.13:12 and 30.11:10, respectively). 60 ...

Page 61

... Not excessive pair skew (1000Base-T only). 1. This is the cable length estimate when the link is active (maximum of 155 m). The values of 0x00 to 0x1f correspond to 0 m—155 increments. The values of 0x20 to 0x3e are reserved for future use, e.g., cable lengths of 160 m—315 m. The result may be invalid for a 10Base-T link. If the result is invalid, a value of 0x3f is returned ...

Page 62

... Airflow 2.5 m/s Airflow 1. For the 128-pin TQFP package operating over the industrial temperature range, the maximum voltage is reduced from 1. 1.05. V. The center tap voltage range is changed to 1.8V only. 2. The part can operate at either 3.3 V (typically for an GMII interface) or 2.5 V (typically for an RGMII interface). ...

Page 63

... All pins tested with IOL=4mA except for the following pins: RXD[3:0]=3mA in MII mode only; MDINT_N and MDIO=9mA, TDO=14mA. 3. All pins tested iwth IOH=3mA except for the following pins: RXD[3:0]=2mA in MII mode; MDINT_N and MDIO=6mA with VOHmin=1.95V, TDO=8mA with VOHmin=1.95V. PHYAD0 and PHYAD1 =5ma with VOHmin=1.95V. ...

Page 64

... Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3.3 V digital - GMII mode) or (2.5 V digital - RGMII mode) Supply Voltage (1.0 V digital) Center Tap Voltage (1 2.5 V analog) Table 59. ET1011C Current Consumption 100Base-TX Parameter Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3 ...

Page 65

... Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3 2.5 V digital) Supply Voltage (1.0 V digital) Center Tap Voltage (1 2.5 V analog) Table 63. ET1011C Current Consumption Low Power Energy Detect (LPED) Parameter Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3 2.5 V digital) Supply Voltage (1 ...

Page 66

... Gigabit Ethernet Transceiver Electrical Specifications (continued) Device Electrical Characteristics Table 64. ET1011C Current Consumption Standby Powerdown and Standby Powerdown with LPED Parameter Supply Voltage (2.5 V analog) Supply Voltage (1.0 V analog) Supply Voltage (3 2.5 V digital) Supply Voltage (1.0 V digital) Center Tap Voltage (1 2.5 V analog) Table 65 ...

Page 67

... September 2007 Timing Specification GMII 1000Base-T Transmit Timing (128-Pin TQFP and 84-Pin MLCC Only) GTX_CLK TXD[7:0] TX_EN TX_ER Table 66. GMII 1000Base-T Transmit Timing Symbol GTX_CLK GTX_CLK Cycle Time CYCLE GTX_CLK GTX_CLK High Time HIGH GTX_CLK GTX_CLK Low Time LOW GTX_CLK GTX_CLK Rise Time ...

Page 68

... Gigabit Ethernet Transceiver Timing Specifications (continued) GMII 1000Base-T Receive Timing (128-Pin TQFP and 84-Pin MLCC Only) RX_CLK RXD[7:0] RX_EN RX_ER Table 67. GMII 1000Base-T Receive Timing Symbol RX_CLK RX_CLK Cycle Time CYCLE RX_CLK RX_CLK High Time HIGH RX_CLK RX_CLK Low Time LOW ...

Page 69

... Tr/Tf Rise/Fall Time (20%—80%) 1. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. To enable internal delay, see MII register 22 bits 2:0. 2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns ± and 40 ns ± 4 ns, respectively. ...

Page 70

... For 10Base-T and 100Base-TX, Tcyc scales to 400 ns ± and 40 ns ± 4 ns, respectively. 3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between. ...

Page 71

... Tr/Tf Rise/Fall Time (20%—80%) 1. This implies that PCB design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. To enable internal delay, see MII register 22 bits 2:0. 2. For 10Base-T and 100Base-TX, Tcyc scales to 400 ns ± and 40 ns ± 4 ns, respectively. ...

Page 72

... For 10Base-T and 100Base-TX, Tcyc scales to 400 ns ± and 40 ns ± 4 ns, respectively. 3. Duty cycle may be shrunk/stretched during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between. ...

Page 73

... September 2007 Timing Specifications (continued) MII 100Base-TX Transmit Timing TX_CLK TXD[3:0] TX_EN TX_ER 1 1. TX_ER is not available on the 68-pin MLCC. Table 72. MII 100Base-TX Transmit Timing Symbol TX_CLK TX_CLK Cycle Time CYCLE TX_CLK TX_CLK High Time HIGH TX_CLK TX_CLK Low Time LOW ...

Page 74

... RX_CLK High Time HIGH RX_CLK RX_CLK Low Time LOW RTX_CLK RX_CLK Rise Time RISE RX_CLK RX_CLK Fall Time FALL RX_CLK MII Output Signal Setup Time to RX_CLK SU RX_CLK MII Output Signal Hold Time to RX_CLK HOLD 74 RX_CLK CYCLE RX_CLK RX_CLK HIGH RX_CLK FALL ...

Page 75

... TX_CLK High Time HIGH TX_CLK TX_CLK Low Time LOW TX_CLK TX_CLK Rise Time RISE TX_CLK TX_CLK Fall Time FALL TX_CLK MII Input Signal Setup Time to TX_CLK SU TX_CLK MII Input Signal Hold Time to TX_CLK HOLD LSI Corporation TX_CLK CYCLE TX_CLK TX_CLK HIGH TX_CLK ...

Page 76

... RX_CLK High Time HIGH RX_CLK RX_CLK Low Time LOW RTX_CLK RX_CLK Rise Time RISE RX_CLK RX_CLK Fall Time FALL RX_CLK MII Output Signal Setup Time to RX_CLK SU RX_CLK MII Output Signal Hold Time to RX_CLK HOLD 76 RX_CLK CYCLE RX_CLK RX_CLK HIGH RX_CLK FALL ...

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... MDIO Signal Hold Time to MDC HOLD MDC MDIO Delay Time from MDC DELAY LSI Corporation MDC CYCLE MDC MDC HIGH MDC SU Figure 25. Serial Management Interface Timing Parameter Gigabit Ethernet Transceiver LOW MDC RISE MDC HOLD MDC DELAY Min Typ Max 100 — ...

Page 78

... RESET_N Deassertion to Configuration Read CFG_READ COMA COMA Pulse Length PULSE_LEN COMA COMA Fall Time FALL COMA COMA Deassertion to SYS_CLK TO_SYS_CLK COMA COMA Deassertion to SYS_CLK Valid TO_SYS_CLK_VALID COMA COMA Deassertion to Configuration Read CFG_READ 78 RESET RESET PULSE_LEN CFG_READ RESET RISE LED pins are Inputs ...

Page 79

... XTAL_1 High Time HIGH XTAL_1 XTAL_1 Low Time LOW XTAL_1 XTAL_1 Rise Time RISE XTAL_1 XTAL_1 Fall Time FALL — XTAL_1 Input Clock Jitter (RMS) — XTAL_1 Input Clock Frequency — XTAL_1 Input Clock Accuracy LSI Corporation XTAL_1 CYCLE XTAL_1 XTAL_1 HIGH LOW ...

Page 80

... TCK Low Time LOW TCK TCK Rise Time RISE TCK TCK Fall Time FALL TCK TDI, TMS Setup Time to TCK SU TCK TDI, TMS Hold Time to TCK HOLD TCK TDO Delay Time from TCK DELAY 80 TCK CYCLE TCK TCK HIGH LOW TCK ...

Page 81

... September 2007 Package Diagram, 128-Pin TQFP Note: Package outlines are unofficial and for reference only GAGE PLANE SEATING PLANE LSI Corporation (Dimensions are in millimeters.) 16.00 ± 0.20 14.00 ± 0.20 PIN #1 IDENTIFIER ZONE 128 103 39 64 DETAIL A DETAIL B 0.50 TYP 0.05/0.15 1 ...

Page 82

... Gigabit Ethernet Transceiver Package Diagram, 84-Pin MLCC Note: Package outlines are unofficial and for reference only. 82 (Dimensions are in millimeters.) September 2007 LSI Corporation ...

Page 83

... September 2007 Package Diagram, 68-Pin MLCC Note: Package outlines are unofficial and for reference only. LSI Corporation (Dimensions are in millimeters.) Gigabit Ethernet Transceiver 83 ...

Page 84

... L- = lead-free, -DT = Tape and Reel. 2. This is revision 3, "C" silicon (not revision 4, "C2" ) and is not recommended for new designs. 84 Description September 2007 1 Part Number Comcode L-ET1011C2-C-D 711017464 L-ET1011C2-C-DT 711017465 L-ET1011C2-CI-D 711017462 L-ET1011C2-CI-DT 711017463 L-ET1011C2-M-D 711017468 L-ET1011C2-M-DT 711017469 L-ET1011C2-MI-D 711017466 L-ET1011C2-MI-DT 711017467 L-ET1011N1C-T-DB 711010940 LSI Corporation ...

Page 85

... LSI Corporation reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. LSI and the LSI logo are trademarks of LSI Corporation. All other brand and product names may be trademarks of their respective companies. TruePHY is a trademark of Agere Systems Inc.. ...

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