EP1S30F780I6N Altera, EP1S30F780I6N Datasheet

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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Revision History
Altera Corporation
Chapter
1
September 2004, v3.1
January 2004, v2.2
October 2003, v2.1
April 2004, v3.0
July 2005, v3.2
July 2003, v2.0
Date/Version
This section provides the data sheet specifications for Stratix
They contain feature definitions of the internal architecture,
configuration and JTAG boundary-scan testing information, DC
operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix devices.
This section contains the following chapters:
The table below shows the revision history for
Chapter 1, Introduction
Chapter 2, Stratix Architecture
Chapter 3, Configuration & Testing
Chapter 4, DC & Switching Characteristics
Chapter 5, Reference & Ordering Information
Minor content changes.
Updated
Main section page numbers changed on first page.
Changed PCI-X to PCI-X 1.0 in
Global change from SignalTap to SignalTap II.
The DSP blocks in
implementation of multipliers that are now “faster than 300 MHz.”
Updated -5 speed grade device information in Table 1-6.
Add -8 speed grade device information.
Format changes throughout chapter.
Section I. Stratix Device
Table 1–6 on page
“Features” on page 1–2
Changes Made
Family Data Sheet
1–5.
“Features” on page
Chapters 1
provide dedicated
1–2.
through 5.
®
Section I–1
devices.

EP1S30F780I6N Summary of contents

Page 1

... July 2005, v3.2 September 2004, v3.1 April 2004, v3.0 January 2004, v2.2 October 2003, v2.1 July 2003, v2.0 Altera Corporation Section I. Stratix Device Family Data Sheet Chapter 1, Introduction Chapter 2, Stratix Architecture Chapter 3, Configuration & Testing Chapter 4, DC & Switching Characteristics Chapter 5, Reference & Ordering Information Changes Made ● ...

Page 2

... Stratix Device Handbook, Volume 1 section. page 2–73. 2–90. 2–92. 2–93. “Clock Multiplication & 2–101. 2–102. “External RAM 2–117. page 2–120. 2–130. 2–131. 2–135. Table 2–18. that support max and min Table 2–30. Table 2–32. Table 2–34. and 2–51. Table 2–37. Altera Corporation ...

Page 3

... July 2005, v1.3 January 2005, v1.2 September 2004, v1.1 April 2003, v1.0 4 January 2006, v3.4 July 2005, v3.3 Altera Corporation Changes Made ● Added reference on page 2-73 to Figures 2-50 and 2-51 for connections. ● Updated ranges for EPLL post-scale and pre-scale dividers on page 2-85. ● ...

Page 4

... Stratix Device Handbook, Volume 1 4–4. 4–6. through Table 4–23 on and V to each table. IH(AC) through Table 4–29 on 4–16. 4–33. 4–20. to Figure 4–4 on page 4–33 Table 4–40 on M512CLKENH to Table 4–41 on page 4–24. 4–35. to Table 4–42 on MRAMCLKENH 4–29. 4–29. Altera Corporation ...

Page 5

... Chapter Date/Version 4 Altera Corporation Changes Made ● Table 4–48 on page 4–30: added rows t and updated symbol names. ● Updated power-up current (ICCINT) required to power a Stratix device on page 4–17. ● Updated Table 4–37 on page 4–22 page 4–27. ● Table 4–49 on page 4–31: added rows t ...

Page 6

... Table 4–38. 4–48 to 4–51, 4–128, and 4–131. to 4–132. Tables 4–117 to 4–119 and 4–122 Figure 4–1. section. and PRE rows in Table 4–47. H row in Table 4–49. row in Table 4–50. section. Tables 4–55 through 4–96. Tables 4–111 to 4–113. Altera Corporation ...

Page 7

... Updated EPLL specification and fast PLL specification in Tables 4- 116 to 4-120. ● Updated reference to device pin-outs on device pin-outs are no longer included in this manual and are now available on the Altera web site. ● No new changes in Stratix Device Handbook v2.0. Stratix Device Family Data Sheet Table 4– ...

Page 8

... Stratix Device Family Data Sheet Section I–8 Stratix Device Handbook, Volume 1 Altera Corporation ...

Page 9

... The following shows the main sections in the Stratix Device Family Data Sheet: Altera Corporation July 2005 ® family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper Section Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1– ...

Page 10

... Support for 133-MHz PCI-X 1 speed-grade devices Support for 100-MHz PCI-X 1 and faster speed-grade devices Support for 66-MHz PCI-X 1 speed-grade devices Support for multiple intellectual property megafunctions from ® Altera MegaCore functions and Altera Megafunction Partners Program (AMPP ) megafunctions SM Support for remote configuration updates TM ...

Page 11

... This parameter lists the total number of 9 × 9-bit multipliers for each device. For the total number of 18 × 18-bit (1) multipliers per device, divide the total number of 9 × 9-bit multipliers by 2. For the total number of 36 × 36-bit multipliers per device, divide the total number of 9 × 9-bit multipliers by 8. Altera Corporation July 2005 EP1S10 EP1S20 ...

Page 12

... Pin 1.27 1,225 35 × 35 ® and ball-grid ® II software can 1,020-Pin 1,508-Pin FineLine FineLine BGA BGA 706 726 773 822 773 1,022 773 1,203 956 Pin 1.27 1,600 40 × 40 Altera Corporation July 2005 ...

Page 13

... BGA BGA EP1S10 -6, -7 EP1S20 -6, -7 EP1S25 -6, -7 EP1S30 -5, -6, -7 EP1S40 -5, -6, -7 EP1S60 -6, -7 EP1S80 -6, -7 Altera Corporation July 2005 672 Pin 780 Pin 1.00 1.00 729 841 27 × × 29 Table 1–6 shows Stratix device speed-grade 484-Pin 672-Pin 780-Pin FineLine FineLine ...

Page 14

... Features 1–6 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 ...

Page 15

... LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for registering input, output, and output-enable signals. When used with Altera Corporation July 2005 2. Stratix Architecture ® ...

Page 16

... LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs IOEs LABs LABs LABs LABs LABs LABs LABs LABs M-RAM Block LABs LABs Altera Corporation July 2005 ...

Page 17

... LE’s register to the adjacent LE’s register within an LAB. The Quartus within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 2–2 Altera Corporation July 2005 M4K RAM M-RAM DSP Block ...

Page 18

... Three-Sided Architecture—Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows shows the direct link connection. Direct link interconnect from adjacent block Direct link interconnect to adjacent block Column Interconnects of Variable Speed & Length Altera Corporation July 2005 ...

Page 19

... LAB-wide clock signals. De-asserting the clock enable signal will turn off the LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high. Altera Corporation July 2005 Local Stratix Architecture Direct link interconnect from ...

Page 20

... LUT chain, register chain, and direct link interconnects. See 2–6 Stratix Device Handbook, Volume 1 interconnect’s inherent low skew TM labclkena1 labclkena2 syncload labclk2 asyncload or labpre Figure 2–5. Figure 2–4 labclr2 addnsub labclr1 synclr Altera Corporation July 2005 ...

Page 21

... This allows the LUT to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the LUT for unrelated Altera Corporation July 2005 Register chain routing from ...

Page 22

... LAB; and the register chain connection— are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, 2–8 Stratix Device Handbook, Volume 1 for more information on LUT chain and Normal mode Dynamic arithmetic mode “MultiTrack Altera Corporation July 2005 ...

Page 23

... LE) data4 Register Feedback Note to Figure 2–6: (1) This signal is only allowed in normal mode if the the end of an adder/subtractor chain. Altera Corporation July 2005 sload sclear (LAB Wide) (LAB Wide) Register chain connection LUT clock (LAB Wide) ena (LAB Wide) ...

Page 24

... LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor. 2–10 Stratix Device Handbook, Volume 1 2–7, the LAB carry-in signal selects either the carry-in0 or Altera Corporation July 2005 ...

Page 25

... the critical path. Only the propagation delay between LAB carry-in generation (LE 5 and LE 10) are now part of the critical path. This feature allows the Stratix architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width. Altera Corporation July 2005 sload sclear (LAB Wide) ...

Page 26

... LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column. 2–12 Stratix Device Handbook, Volume 1 shows the carry-select circuitry in an LAB for a 10-bit full ™ Altera Corporation July 2005 ...

Page 27

... The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOT- gate push-back technique. Stratix devices support simultaneous preset/ Altera Corporation July 2005 LAB Carry-In Carry-In0 ...

Page 28

... Stratix Device Handbook, Volume 1 Direct link interconnects between LABs and adjacent blocks. R4 interconnects traversing four blocks to the right or left. R8 interconnects traversing eight blocks to the right or left. R24 row interconnects for high-speed access across the length of the device. technology. The MultiTrack TM Altera Corporation July 2005 ...

Page 29

... LABs in a row are similar to the R4 connections shown in to the right or left, not four. Like R4 interconnects, R8 interconnects can drive and be driven by all types of architecture blocks. R8 interconnects Altera Corporation July 2005 Adjacent LAB can C4, C8, and C16 Drive onto Another ...

Page 30

... C4 interconnects traversing a distance of four blocks in up and down direction C8 interconnects traversing a distance of eight blocks in up and down direction C16 column interconnects for high-speed vertical routing through the device Figure 2–10 shows the LUT chain and register chain Altera Corporation July 2005 ...

Page 31

... IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. Altera Corporation July 2005 Local Interconnect Routing Among LEs ...

Page 32

... LAB's C4 interconnect Note to Figure 2–11: (1) Each C4 interconnect can drive either up or down four rows. 2–18 Stratix Device Handbook, Volume 1 Note (1) Local Interconnect C4 Interconnect Drives Local and R4 Interconnects up to Four Rows C4 Interconnect Driving Up LAB C4 Interconnect Driving Down Altera Corporation July 2005 ...

Page 33

... These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[7..0]. Altera Corporation July 2005 Stratix Architecture Figure 2–11 with the 2– ...

Page 34

... R8 Interconnect R24 Interconnect v C4 Interconnect v C8 Interconnect C16 Interconnect M512 RAM v Block v M4K RAM Block M-RAM Block v DSP Blocks Column IOE Row IOE 2–20 Stratix Device Handbook, Volume 1 shows the Stratix device’s routing scheme. Destination Altera Corporation July 2005 ...

Page 35

... True dual-port memory mixed width support Power-up conditions Register clears Mixed-port read- during-write Altera Corporation July 2005 Table 2–3 shows the size and features of the different M512 RAM Block M4K RAM Block (32 × 18 Bits) (128 × 36 Bits) (1) ...

Page 36

... B data [ ] B address [ ] B wren B clock B clocken aclr B Altera Corporation July 2005 ...

Page 37

... The memory blocks also enable mixed-width data ports for reading and writing to the RAM ports in dual-port RAM configuration. For example, the memory block can be written in ×1 mode at port A and read out in ×16 mode from port B. Altera Corporation July 2005 Chapter 2, TriMatrix Embedded Memory Blocks in of the ...

Page 38

... You can also use parity-size data words to store user-specified control bits. In the M4K and M-RAM blocks, byte enables are also available for data input masking during write operations. 2–24 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 ...

Page 39

... The shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. TriMatrix memory block in the shift register mode. Altera Corporation July 2005 Stratix Architecture Figure 2–14 shows the 2– ...

Page 40

... The Quartus II software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. You can also manually assign the memory to a specific block size or a mixture of block sizes. 2–26 Stratix Device Handbook, Volume Number of Taps w w Altera Corporation July 2005 ...

Page 41

... By using the mixed-width support in combination with DDR I/O standards, the block can function as a SERDES to support low-speed serial I/O standards using global or regional clocks. See dedicated SERDES in Stratix devices. Altera Corporation July 2005 Simple dual-port RAM Single-port RAM FIFO ...

Page 42

... M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. RAM block to logic array interface. 2–28 Stratix Device Handbook, Volume 1 Figure 2–15 shows the M512 RAM block Figure 2–16 shows the M512 Altera Corporation July 2005 ...

Page 43

... Figure 2–15. M512 RAM Block Control Signals Dedicated 8 Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Altera Corporation July 2005 outclocken inclocken inclock outclock Stratix Device Handbook, Volume 1 Stratix Architecture wren outclr rden inclr 2–29 ...

Page 44

... M512 RAM Block Control Signals datain address Clocks 2 LAB Row Clocks True dual-port RAM Simple dual-port RAM Single-port RAM FIFO ROM Shift register R4 and R8 Interconnects Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB Altera Corporation July 2005 ...

Page 45

... When the M4K RAM block is configured as a shift register block, you can create a shift register up to 4,608 bits (w × m × n). Altera Corporation July 2005 Tables 2–5 and 2–6 summarize the possible M4K RAM block Write Port 128 × 32 512 × 9 256 × 18 ...

Page 46

... Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in × 16 and × 32 modes. Figure summarizes the byte Notes (1), (2) datain ×36 [8..0] [17..9] – [26..18] – [35..27] 2–17. Figure 2–18 shows Altera Corporation July 2005 ...

Page 47

... Figure 2–18. M4K RAM Block LAB Row Interface C4 and C8 Interconnects 10 Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB M4K RAM Block Local Interconnect Region Altera Corporation July 2005 alcr_a renwe_b renwe_a alcr_b clocken_b dataout M4K RAM Block Byte enable Control ...

Page 48

... Stratix Device Handbook, Volume 1 True dual-port RAM Simple dual-port RAM Single-port RAM FIFO RAM Tables 2–8 64K × 9 32K × × × × × 72 × 144 and 2–9 summarize the Write Port 16K × × × 144 Altera Corporation July 2005 ...

Page 49

... The byte enables are available for the ×18, ×36, and ×72 modes. In the ×144 simple dual-port mode, the two sets of byteena signals (byteena_a and byteena_b) are combined to form the necessary 16 byte enables. Table 2–10. Byte Enable for M-RAM Blocks byteena[3..0] Altera Corporation July 2005 Port A 64K × × ...

Page 50

... Byte enables can be used in the same manner with 8-bit words, i.e., in × 16, × 32, × 64, and × 128 modes. Figure Notes (1), (2) datain ×144 [8..0] [17..9] [26..18] [35..27] [44..36] [53..45] [62..54] [71..63] [80..72] [89..81] [98..90] [107..99] [116..108] [125..117] [134..126] [143..135] 2–19. Altera Corporation July 2005 ...

Page 51

... B, and the bottom side has another 72 data inputs and 72 data outputs for port A. shows an example floorplan for the EP1S60 device and the location of the M-RAM interfaces. Altera Corporation July 2005 8 clocken_b clocken_a ...

Page 52

... M-RAM block are possible from the left adjacent LABs for M-RAM 2–38 Stratix Device Handbook, Volume 1 Note (1) M-RAM Block M-RAM Block M4K LABs Blocks Independent M-RAM blocks interface to top, bottom, and side facing device perimeter for easy access to horizontal I/O pins. M-RAM Block M-RAM Block DSP Blocks Altera Corporation July 2005 ...

Page 53

... LABs for M-RAM blocks facing to the right. For column interfacing, every M-RAM column unit connects to the right and left column lines, allowing each M-RAM column unit to communicate directly with three columns of LABs. block and the logic array. Altera Corporation July 2005 Figures 2–21 through 2–23 ...

Page 54

... Notes (1), M512 RAM Block Columns Port B M-RAM Block Port (2) LABs in Column M-RAM Boundary Column Interface Block Drives to and from C4 and C8 Interconnects B5 B6 Column Interface Block A5 A6 Allows LAB Columns to Drive datain and dataout to and from M-RAM Block Altera Corporation July 2005 ...

Page 55

... Figure 2–22. M-RAM Row Unit Interface to Interconnect Direct Link Interconnects Altera Corporation July 2005 C4 and C8 Interconnects R4 and R8 Interconnects LAB Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region Stratix Device Handbook, Volume 1 Stratix Architecture M-RAM Block addressa addressb renwe_a ...

Page 56

... TriMatrix Memory Figure 2–23. M-RAM Column Unit Interface to Interconnect 2–42 Stratix Device Handbook, Volume 1 C4 and C8 Interconnects LAB LAB 12 datain M-RAM Block LAB M-RAM Block to LAB Row Interface Block Interconnect Region Column Interface Block 12 dataout Altera Corporation July 2005 ...

Page 57

... B6 and A1 to A6). It also shows the address and control signal input connections to the row units (R1 to R11). Table 2–12. M-RAM Row & Column Interface Unit Signals Unit Interface Block Altera Corporation July 2005 shows the input and output data signal connections for the Input SIgnals R1 addressa[7 ...

Page 58

... B controls all registers on the port B side. Each port, A and B, also supports independent clock enables and asynchronous clear signals for port A and B registers. independent clock mode. 2–44 Stratix Device Handbook, Volume 1 Figure 2–24 shows a TriMatrix memory block in Altera Corporation July 2005 ...

Page 59

... Figure 2–24. Independent Clock Mode Notes to (1) (2) Altera Corporation July 2005 Figure 2–24 All registers shown have asynchronous clear ports. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Stratix Architecture ...

Page 60

... The other clock controls the block’s data output registers. Each memory block port also supports independent clock enables and asynchronous clear signals for input and output registers. clock mode. 2–46 Stratix Device Handbook, Volume 1 Figures 2–25 and 2–26 show the memory block in input/output Altera Corporation July 2005 ...

Page 61

... Figure 2–25. Input/Output Clock Mode in True Dual-Port Mode Notes to (1) (2) Altera Corporation July 2005 Figure 2–25: All registers shown have asynchronous clear ports. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. ...

Page 62

... Read Address D Q ENA Data Out Byte Enable D Q ENA Write Address D Q ENA Read Enable D Q ENA Write D Q Write Enable Pulse ENA Generator (2) 512 ´ MultiTrack Interconnect D Q ENA Altera Corporation July 2005 ...

Page 63

... The memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. memory block in read/write clock mode. Altera Corporation July 2005 Stratix Architecture Figure 2–27 shows a 2– ...

Page 64

... D Q Data In 2,048 × 2 ENA 4,096 × 1 Data Out D Q Read Address ENA Write Address D Q ENA Byte Enable D Q ENA Read Enable D Q ENA Write D Q Write Enable Pulse ENA Generator (2) To MultiTrack Interconnect D Q ENA Altera Corporation July 2005 ...

Page 65

... Note to Figure 2–28: (1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. Altera Corporation July 2005 RAM/ROM 256 × 16 1,024 × Data In 2,048 × 2 ENA 4,096 × 1 ...

Page 66

... This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions. shows one of the columns with surrounding LAB rows. Table 2–13). Each Altera Corporation July 2005 ...

Page 67

... Figure 2–29. DSP Blocks Arranged in Columns Altera Corporation July 2005 DSP Block Column DSP Block 8 LAB Rows Stratix Device Handbook, Volume 1 Stratix Architecture 2–53 ...

Page 68

... The total number of multipliers for each device is not the sum of all the multipliers. The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations. shows the top-level diagram of the DSP block configured for Figure 2–31 Notes (1), (2) Total 18 × 18 Total 36 × 36 Multipliers Multipliers shows the 9 × 9-bit multiplier Altera Corporation July 2005 ...

Page 69

... Q ENA CLRN D Q ENA CLRN D Q ENA CLRN Optional Serial Shift Register Outputs to Next DSP Block the Column ENA CLRN Altera Corporation July 2005 Multiplier Stage Optional Stage Configurable as Accumulator or Dynamic Adder/Subtractor D Q ENA CLRN Adder/ Subtractor/ Accumulator ENA CLRN D Q ENA ...

Page 70

... ENA CLRN D Q ENA CLRN D Q ENA CLRN D Q ENA CLRN D Q ENA CLRN D Q ENA CLRN Adder/ Subtractor ENA CLRN D Q ENA CLRN D Q ENA CLRN Summation Output Selection D Q Multiplexer ENA CLRN Summation To MultiTrack Interconnect Altera Corporation July 2005 ...

Page 71

... Figure 2–32. Multiplier Sub-Block within Stratix DSP Block shiftin B Data A ENA Data B ENA shiftout B shiftout A Note to Figure 2–32: (1) These signals can be unregistered or registered once to match data path pipelines if required. Altera Corporation July 2005 Multiplier block Adder/output block sign_a (1) sign_b (1) aclr[3..0] clock[3..0] ena[3..0] shiftin ...

Page 72

... LAB LEs. You implement all the filter circuitry within the DSP block and its routing resources, saving LE and general routing resources for general logic. External registers are needed for shift register inputs when using 36 × 36-bit multipliers. 2–58 Stratix Device Handbook, Volume 1 Figure 2–33, to Altera Corporation July 2005 ...

Page 73

... Figure 2–33. Multiplier Sub-Blocks Using Input Shift Register Connections Note (1) Data A Data B Note to (1) Altera Corporation July 2005 D Q ENA CLRN D Q ENA CLRN Data B Data ENA CLRN D Q ENA CLRN Data A Data ENA CLRN D Q ENA CLRN Figure 2–33: Either Data A or Data B input can be set to a parallel input for constant coefficient multiplication ...

Page 74

... Table 2–15. Multiplier Signed Representation 2–60 Stratix Device Handbook, Volume 1 shows the summary of input register modes for the DSP block. 9 × Data A Data B Unsigned Unsigned Unsigned Signed Signed Unsigned Signed Signed 18 × × Table 2–15. The Result Unsigned Signed Signed Signed Altera Corporation July 2005 ...

Page 75

... You can configure the adder/output block to use output registers in any mode, and must use output registers for the accumulator. The system cannot use adder/output blocks independently of the multiplier. Altera Corporation July 2005 Figure 2–34 shows the adder and output stages. ...

Page 76

... These signals are either not registered, registered once, or registered twice to match the data path pipeline. 2–62 Stratix Device Handbook, Volume 1 Note (1) Accumulator Feedback Adder/ Subtractor/ Summation Adder/ Subtractor/ Accumulator Feedback × 18-bit mode × 9-bit mode, there are four adder/subtractor overflow0 Output Selection Multiplexer Output Register Block overflow1 Altera Corporation July 2005 ...

Page 77

... In 9 × 9-bit mode, there are two summation blocks providing the sums of two sets of four 9 × 9-bit multipliers × 18-bit mode, there is one summation providing the sum of one set of four 18 × 18-bit multipliers. Altera Corporation July 2005 Stratix Architecture Figure 2–34. The Stratix Device Handbook, Volume 1 2– ...

Page 78

... DSP block. See 2–64 Stratix Device Handbook, Volume 1 Simple multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder Each DSP block can only support one mode. Mixed modes in the same DSP block is not supported. Figure 2–35. Altera Corporation July 2005 ...

Page 79

... The input shift register feature is not available for the 36 × 36-bit multiplier × 36-bit mode, the device can use the register that is normally a multiplier-result-output register as a pipeline stage for the 36 × 36-bit multiplier. mode. Altera Corporation July 2005 aclr clock ena ...

Page 80

... These signals are not registered, registered once, or registered twice for latency to match the pipeline. 2–66 Stratix Device Handbook, Volume ENA CLRN D Q ENA 36 × 36 Multiplier Adder CLRN signa (2) signb ( ENA CLRN D Q ENA CLRN Data Out D Q ENA CLRN Altera Corporation July 2005 ...

Page 81

... These signals are not registered, registered once, or registered twice for latency to match the data path pipeline. Two-Multipliers Adder Mode The two-multipliers adder mode uses the adder/subtractor/accumulator block to add or subtract the outputs of the multiplier block, which is useful for applications such as FFT functions and complex FIR filters. A Altera Corporation July 2005 Figure 2–37), the DSP block drives D ...

Page 82

... Stratix Device Handbook, Volume jb) × jd) = [(a × c) – (b × d × [(a × × c Figure 2–39 Figure 2–38 shows an 18-bit DSP Block 37 (A × C) − (B × D) Subtractor (Real Part × × C) Adder (Imaginary Part) shows the four multipliers Altera Corporation July 2005 ...

Page 83

... B shiftout A Notes to Figure 2–39: (1) These signals are not registered or registered once to match the data path pipeline. (2) These signals are not registered, registered once, or registered twice for latency to match the data path pipeline. Altera Corporation July 2005 D Q ENA Adder/Subtractor CLRN D Q ...

Page 84

... Four multipliers with four product outputs Two multiply and accumulate (52 bits) Two sums of two multiplier products each One sum of four multiplier products each 36 × 36 (1) One multiplier with one product output – – – Altera Corporation July 2005 ...

Page 85

... LAB though direct link interconnects. All 18 outputs can drive to all types of row and column routing. Outputs can drive right- or left-column routing. and Figure 2–40. DSP Block Interconnect Interface Altera Corporation July 2005 2–41 show the DSP block interfaces to LAB rows. DSP Block OA[17 ...

Page 86

... Stratix Device Handbook, Volume 1 R4 and R8 Interconnects DSP Block Row Structure Control 18 [17..0] Row Interface Block 18 Inputs per Row Nine Direct Link Outputs Direct Link Interconnect to Adjacent LABs from Adjacent LAB 18 LAB 9 18 [17..0] 18 Outputs per Row Altera Corporation July 2005 ...

Page 87

... EP1S60, and EP1S80 devices). These clocks are organized into a hierarchical clock structure that allows for clocks per device region with low skew and delay. This hierarchical clocking scheme provides unique clock domains within Stratix devices. Altera Corporation July 2005 Control Signals Data Inputs ...

Page 88

... CLK pins driving global clock networks. 2–74 Stratix Device Handbook, Volume 1 Figure 2–42. Enhanced and fast PLL outputs can also drive Figure 2–42 shows the Altera Corporation July 2005 ...

Page 89

... RCLK cannot be driven by internal logic. The CLK clock pins symmetrically drive the RCLK networks within a particular quadrant, as shown in from PLLs and CLK pins. Altera Corporation July 2005 Note (1) CLK[15..12] Global Clock [15..0] CLK[7 ...

Page 90

... Stratix Device Handbook, Volume 1 RCLK[2..3] CLK[3..0] CLK[7..4] RCLK[6..7] RCLK[12..13] Figure 2–45). Dual-purpose FCLK pins drive the fast RCLK[11..10] CLK[15..12] RCLK[9..8] CLK[11..8] RCLK[14..15] Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins or PLLs within that Quadrant Figure 2–44). In EP1S30 and Altera Corporation July 2005 ...

Page 91

... Figure 2–44. EP1S25, EP1S20 & EP1S10 Device Fast Clock Pin Connections to Fast Regional Clocks Notes to (1) (2) Altera Corporation July 2005 FCLK[1..0] 2 (1), (2) 2 FCLK[1..0] FCLK[1..0] 2 (1), (2) 2 FCLK[3..2] Figure 2–44: This is a set of two multiplexers. In addition to the FCLK pin inputs, there is also an input from the I/O interconnect. ...

Page 92

... FCLK0 (1), (2) (1), (2) (1), (2) (1), (2) (1), (2) (1), (2) FCLK3 FCLK2 Figure 2–45: This is a set of two multiplexers. In addition to the FCLK pin inputs, there is also an input from the I/O interconnect. FCLK7 FCLK6 (1), (2) fclk[1..0] (1), (2) FCLK5 FCLK4 Figure 2–46. Altera Corporation July 2005 ...

Page 93

... I/O clock signals chosen from the 22 quadrant or half-quadrant clock resources. quadrant relationship to the I/O clock regions, respectively. The vertical regions (column pins) have less clock delay than the horizontal regions (row pins). Altera Corporation July 2005 Clocks Available to a Quadrant or Half-Quadrant Clock [21..0] Figures 2– ...

Page 94

... Figure 2–47. EP1S10, EP1S20 & EP1S25 Device I/O Clock Groups 8 IO_CLKH[7..0] 8 IO_CLKG[7..0] 8 2–80 Stratix Device Handbook, Volume 1 IO_CLKA[7..0] IO_CLKB[7.. Clocks in 22 Clocks in the Quadrant the Quadrant 22 Clocks in 22 Clocks in the Quadrant the Quadrant 8 IO_CLKF[7..0] IO_CLKE[7..0] 8 I/O Clock Regions IO_CLKC[7..0] 8 IO_CLKD[7..0] 8 Altera Corporation July 2005 ...

Page 95

... With features such as clock switchover, spread spectrum clocking, programmable bandwidth, phase and delay control, and PLL reconfiguration, the Stratix device’s enhanced PLLs provide you with complete control of your clocks and system timing. The fast PLLs Altera Corporation July 2005 IO_CLKB[7:0] IO_CLKC[7:0] ...

Page 96

... EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA 2–82 Stratix Device Handbook, Volume 1 Table 2–18 Fast PLLs (3) (3) ( (3) (3) ( shows the PLLs available for Enhanced PLLs 5(1) 6(1) 11(2) 12( ( v(3) v(3) ( ® package. Altera Corporation July 2005 ...

Page 97

... Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout. (8) Every Stratix device has two enhanced PLLs with one single-ended or differential external feedback input per PLL. Altera Corporation July 2005 shows the enhanced PLL and fast PLL features in Stratix Enhanced PLL m/(n × ...

Page 98

... PLLs & Clock Networks Figure 2–49 floorplan. Figure 2–49. PLL Locations 7 FPLL7CLK 1 CLK[3..0] 2 PLLs FPLL8CLK 8 2–84 Stratix Device Handbook, Volume 1 shows a top-level diagram of the Stratix device and PLL CLK[15..12 CLK[7..4] 10 FPLL10CLK 4 CLK[8..11 FPLL9CLK Altera Corporation July 2005 ...

Page 99

... The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL. Figure 2–51 outputs and top CLK pins. Altera Corporation July 2005 shows the global and regional clocking from the PLL outputs Global ...

Page 100

... The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11 and 12. 2–86 Stratix Device Handbook, Volume 1 (1) (2) (1) E[0..3] PLL 5 PLL PLL 6 PLL 12 (1) (1) (2) Note (1) (2) RCLK10 RCLK11 G12 G13 G14 G15 RCLK12 RCLK13 (2) Altera Corporation July 2005 ...

Page 101

... This connection is only available on EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and PLLs 6 and 12 are adjacent. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11 and 12. Altera Corporation July 2005 Figure 2–52 shows a diagram of the enhanced PLL. ...

Page 102

... Clock-sense circuitry automatically switches from the primary to secondary clock for PLL reference when the primary clock signal is not present. 2–88 Stratix Device Handbook, Volume 1 Figure 2–53 shows a block diagram of the switchover × (m/n). IN Altera Corporation July 2005 ...

Page 103

... Figure 2–53. Clock Switchover Circuitry SMCLKSW INCLK0 INCLK1 There are two possible ways to use the clock switchover feature. ■ ■ Altera Corporation July 2005 Clock Switch-Over Sense State Machine MUXOUT n Counter Enhanced PLL Use automatic switchover circuitry for switching between inputs of the same frequency ...

Page 104

... PLL using a input shift clock rate of 22 MHz. The charge pump, loop filter components, and phase shifting using VCO phase taps cannot be dynamically adjusted. 2–90 Stratix Device Handbook, Volume 1 shows a diagram of the overall dynamic PLL control feature CO Altera Corporation July 2005 ...

Page 105

... A low- bandwidth PLL will take longer to lock, but it will attenuate all high- frequency jitter components. The Quartus II software can adjust PLL characteristics to achieve the desired bandwidth. The programmable Altera Corporation July 2005 Charge Loop ...

Page 106

... Differential SSTL and HSTL outputs are implemented using 2 single-ended output buffers which are programmed to have opposite polarity. In Quartus II software, simply assign the appropriate differential I/O standard and the software will implement the inversion. See 2–92 Stratix Device Handbook, Volume 1 Figure 2–55. Altera Corporation July 2005 ...

Page 107

... EP1S10, EP1S20, and EP1S25 devices in 672-pin BGA and 484- and 672-pin FineLine BGA packages only have two pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n). (4) Differential SSTL and HSTL outputs are implemented using two single-ended output buffers, which are programmed to have opposite polarity. Altera Corporation July 2005 pll_out0p (3), (4) (3) pll_out0n (3), (4) ...

Page 108

... PCI-X 1.0 LVPECL 3.3-V PCML LVDS HyperTransport technology Differential HSTL Differential SSTL 3.3-V GTL 3.3-V GTL+ 1.5-V HSTL Class I 2–94 Stratix Device Handbook, Volume 1 I/O Standard INCLK Table 2–20 shows which I/O Input Output FBIN PLLENABLE EXTCLK Altera Corporation July 2005 ...

Page 109

... For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n. Stratix devices can drive any enhanced PLL driven through the global clock or regional clock network to any general I/O pin as an external output clock. The jitter on the output clock is not guaranteed for these cases. Altera Corporation July 2005 I/O Standard INCLK v ...

Page 110

... Stratix Device Handbook, Volume 1 Zero delay buffer: The external clock output pin is phase-aligned with the clock input pin for zero delay. Altera recommends using the same I/O standard on the input clock and the output clocks for optimum performance. External feedback: The external feedback input pin, FBIN, is phase- aligned with the clock input, CLK, pin ...

Page 111

... Normal or Zero Delay Buffer Mode Δt eOUTPUT Δt gOUTPUT Δt lOUTPUT Note to (1) Altera Corporation July 2005 shows the combined delay for each output for normal or zero , Δ Δ for a single output can range from – ns. The total OUTPUT 2–21). This effect occurs because the Δt = Δ ...

Page 112

... Advanced Clear & Enable Control There are several control signals for clearing and enabling PLLs and their outputs. You can use these signals to control PLL resynchronization and gate PLL output clocks for low-power applications. 2–98 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 ...

Page 113

... This feature is useful for applications that require a low power or sleep mode. Upon re-enabling, the PLL does not need a Altera Corporation July 2005 PLL Reconfiguration or Clock switchover enables in the design. ...

Page 114

... Figure 2–57. extclkena Signals COUNTER OUTPUT CLKENA CLKOUT Fast PLLs Stratix devices contain up to eight fast PLLs with high-speed serial interfacing ability, along with general-purpose features. shows a diagram of the fast PLL. 2–100 Stratix Device Handbook, Volume 1 Figure 2–58 Altera Corporation July 2005 ...

Page 115

... VCO frequency to drive the SERDES. When used for clocking the SERDES, the m counter can range from 1 to 30. The VCO frequency is equal to f 300 and 1000 MHz. Altera Corporation July 2005 VCO Phase Selection Selectable at each PLL Output Port ...

Page 116

... HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II SSTL-18 Class I SSTL-18 Class II SSTL-2 Class I 2–102 Stratix Device Handbook, Volume 1 Figure 2–50 on page 2–85. shows the I/O standards supported by fast PLL input pins. I/O Standard Input INCLK PLLENABLE Altera Corporation July 2005 ...

Page 117

... You can perform phase shifting in time units with a resolution range of 125 to 416.66 ps. This resolution is a function of the VCO period, with the finest step being equal to an eighth (×0.125) of the VCO period. Altera Corporation July 2005 I/O Standard shows the performance on each of the fast PLL clock inputs ...

Page 118

... Output drive strength control Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Double-data rate (DDR) Registers Figure 2–59 shows the Stratix IOE structure. The “High- 2–130. Altera Corporation July 2005 ...

Page 119

... There are up to four IOEs per row I/O block and six IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 2–60 Figure 2–61 Altera Corporation July 2005 OE Register D Q ...

Page 120

... I/O Interconnect Interconnects I/O Block Local Interconnect io_dataouta[3..0] io_dataoutb[3..0] Direct Link Interconnect to Adjacent LAB 16 Control Signals from I/O Interconnect ( Data & Control Signals from Logic Array (2) 28 Horizontal I/O Block Horizontal I/O Block Contains io_clk[7: Four IOEs Altera Corporation July 2005 ...

Page 121

... The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear signals io_cclr[5..0]. Altera Corporation July 2005 Vertical I/O Block 16 ...

Page 122

... To Logic Array io_datain1 io_coe io_cce_in io_cce_out From Logic io_cclr Array io_cclk io_dataout0 io_dataout1 2–108 Stratix Device Handbook, Volume 1 2–73). To Other IOEs oe ce_in ce_out Control aclr/apreset Signal Selection sclr/spreset clk_in clk_out Figure 2–62 illustrates the IOE Altera Corporation July 2005 ...

Page 123

... The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects. shows the IOE in bidirectional configuration. Altera Corporation July 2005 Figure 2–63 illustrates the control signal io_bclk[3 ...

Page 124

... Input Register D Q Input Clock ENA Enable Delay CLRN/PRN Output t Delay ZX OE Register t Delay CO V CCIO Optional PCI Clamp V CCIO Programmable Pull-Up Resistor Slew Control Input Pin to Logic Array Delay Bus-Hold Input Pin to Circuit Input Register Delay Altera Corporation July 2005 ...

Page 125

... This allows both bits of data to be synchronous with the same clock edge (either rising or falling). Figure 2–65 the DDR input timing diagram. Altera Corporation July 2005 delay to the output pin, which is required for ZBT interfaces. ZX shows the programmable delays for Stratix devices. ...

Page 126

... Input Pin to Input Register Delay Input Register D Q ENA CLRN/PRN Output Clock Enable Delay Chip-Wide Reset Input Register D Q ENA CLRN/PRN VCCIO Optional PCI Clamp To DQS Local Bus (3) VCCIO Programmable Pull-Up Resistor Bus-Hold Circuit Latch D Q ENA CLRN/PRN Altera Corporation July 2005 ...

Page 127

... One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. shows the DDR output timing diagram. Altera Corporation July 2005 ...

Page 128

... Pin Delay ENA CLRN/PRN Drive Strength Control Open-Drain Output Output Register Logic Array to Output D Q Register Delay ENA CLRN/PRN Output t Delay ZX OE Register t Delay CO V CCIO Optional PCI Clamp V CCIO Programmable Pull-Up Resistor clk Slew Control Bus-Hold Circuit Altera Corporation July 2005 ...

Page 129

... For information on memory controller megafunctions for Stratix devices, see the Altera web site (www.altera.com). See AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices for more information on DDR SDRAM interface in Stratix. Also see AN 349: QDR SRAM Controller Reference Design for Stratix & ...

Page 130

... Table 2–25 have -7 Speed Grade -8 Speed Grade Flip- Wire- Flip- Wire- Chip Bond Chip Bond 133 100 100 100 133 100 100 100 (5) (5) (5) (5) 133 100 100 100 133 100 100 100 167 167 133 133 Altera Corporation July 2005 ...

Page 131

... BGA 672-pin FineLine BGA 484-pin FineLine BGA 780-pin FineLine BGA EP1S20 484-pin FineLine BGA 672-pin BGA 672-pin FineLine BGA 780-pin FineLine BGA Altera Corporation July 2005 Maximum Clock Rate (MHz) I/O Standard -5 Speed Grade SSTL-2 167 SSTL-2 150 1.5-V HSTL 133 1 ...

Page 132

... DQS pins located on the bottom of the device. All 10 delay elements (DQS signals) on either the top or bottom of the device 2–118 Stratix Device Handbook, Volume 1 (Part Note (1) Number of ×8 Number of ×16 Groups Groups 16 ( Number of ×32 Groups Altera Corporation July 2005 ...

Page 133

... SSTL-3 Class I and II, SSTL-2 Class I and II, HSTL Class I and II, and 3.3-V GTL+ support a minimum setting, the lowest drive strength that guarantees the I provides signal slew rate control to reduce system noise and signal overshoot. Altera Corporation July 2005 Figure 2–69 illustrates the phase-shift reference circuit Phase ...

Page 134

... Compliant” for 3.3-V PCI, 3.3-V PCI-X 1.0, and Compact PCI I/O standards. Stratix devices support series on-chip termination (OCT) using programmable drive strength. For more information, contact your Altera Support Representative. Open-Drain Output Stratix devices provide an optional open-drain (equivalent to an open- collector) output for each I/O pin ...

Page 135

... This information is provided for each V The bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration. Altera Corporation July 2005 shows bus hold support for different pin types. Pin Type ...

Page 136

... AGP (1× and 2×) LVDS LVPECL 3.3-V PCML HyperTransport Differential HSTL (on input/output clocks only) Differential SSTL (on output column clock pins only) GTL/GTL+ 1.5-V HSTL Class I and II CCIO shows which pin types support Programmable Weak Pull-Up Resistor (1) Altera Corporation July 2005 ...

Page 137

... Notes to Table 2–31: (1) This I/O standard is only available on input and output clock pins. (2) This I/O standard is only available on output column clock pins. Altera Corporation July 2005 1.8-V HSTL Class I and II SSTL-3 Class I and II SSTL-2 Class I and II SSTL-18 Class I and II CTT describes the I/O standards supported by Stratix devices. ...

Page 138

... SSTL and HSTL. 2–124 Stratix Device Handbook, Volume 1 Table 2–31 except PCI I/O pins or PCI-X 1.0, GTL, Table 2–32 shows I/O standard support for each I/O bank. Figure 2–70. The four I/O Altera Corporation July 2005 ...

Page 139

... This will correspond to a top-down view for non-flip-chip packages, but will be a reverse view for flip-chip packages. (2) Figure 2– graphic representation only. See the device pin-outs on the web (www.altera.com) and the Quartus II software for exact locations. (3) Banks 9 through 12 are enhanced PLL external clock output banks. ...

Page 140

... SSTL-18 Class I SSTL-18 Class II SSTL-2 Class I SSTL-2 Class II SSTL-3 Class I 2–126 Stratix Device Handbook, Volume 1 shows I/O standard support for each I/O bank. Left & Right Banks ( & & Enhanced PLL External Clock Output Banks (9, 10, 11 & 12 Altera Corporation July 2005 ...

Page 141

... The internal termination is designed using transistors in the linear region of operation. Stratix devices support internal differential termination with a nominal resistance value of 137.5 Ω for LVDS input receiver buffers. LVPECL signals require an external termination resistor. device with differential termination. Altera Corporation July 2005 Left & Right Banks ( & & ...

Page 142

... Stratix device differential termination support. Top & Bottom I/O Standard Support Banks ( & 8) LVDS shows the termination support for different pin types. Pin Type Ω ± Receiving Device with Differential Termination + R D Ð Left & Right Banks ( & Altera Corporation July 2005 ...

Page 143

... The Stratix VCCINT pins must always be connected to a 1.5-V power supply. With a 1.5-V V 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V, 2.5-V, or 3.3-V power supply, depending on the output requirements. Altera Corporation July 2005 Pad Package Ball 0.3 Ω ...

Page 144

... PLLs in the EP1S30 to EP1S80 devices to multiply reference clocks and drive high-speed differential SERDES channels. f See the Stratix device pin-outs at www.altera.com for additional high speed DIFFIO pin information for Stratix devices. 2–130 Stratix Device Handbook, Volume 1 summarizes Stratix MultiVolt I/O support. ...

Page 145

... FineLine BGA 672-pin BGA 780-pin FineLine BGA Transmitter EP1S20 484-pin FineLine BGA Transmitter 672-pin FineLine BGA 672-pin BGA 780-pin FineLine BGA Transmitter Altera Corporation July 2005 shows the number of channels that each fast PLL can clock in Maximum Transmitter/ Total Speed Receiver ...

Page 146

... Transmitter/ Total Speed Receiver Channels (Mbps) (2) (4) Transmitter 56 624 (3) 624 Receiver 58 624 (4) (3) 624 (2) (4) 70 840 840 (3) (4) Receiver 66 840 (3) 840 Transmitter (2) 78 840 (4) 840 (3) (4) Receiver 78 840 840 (3) Note (1) Center Fast PLLs PLL 1 PLL 2 PLL 3 PLL Altera Corporation July 2005 ...

Page 147

... Channels 780-pin Transmitter 68 FineLine (4) BGA Receiver 66 Altera Corporation July 2005 The receiver PLL is only clocking receive channels (no resources for the transmitter) If all channels can fit in one I/O bank Note (1) Maximum Center Fast PLLs Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 ...

Page 148

... Note (1) Maximum Center Fast PLLs Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps) 840 (5) ( 840 840 840 (5) (8) Corner Fast PLLs (2 (2) (2) (3) ( (2) (2) ( (2) (2) (3) ( (2) (2) (3) (3) Corner Fast PLLs (2), ( Altera Corporation July 2005 ...

Page 149

... Total Package Receiver Channels 956-pin Transmitter 80 (40) BGA (4) (7) Receiver 80 1,020-pin Transmitter 92 (12) FineLine (4) (7) BGA Receiver 90 (10) (7) Altera Corporation July 2005 Note (1) Maximum Center Fast PLLs Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps) 840 (2) (4) ( 840 (5) (8) ...

Page 150

... For the location of these channels, see the device pin-outs at www.altera.com. (8) See the Stratix device pin-outs at www.altera.com. Channels marked “high” speed are 840 MBps and “low” speed channels are 462 MBps. The high-speed differential I/O circuitry supports the following high speed I/O interconnect standards and applications: ■ ...

Page 151

... An external pin or global or regional clock can drive the fast PLLs, which can output up to three clocks: two multiplied high-speed differential I/O clocks to drive the SERDES block and/or external pin, and a low-speed clock to drive the logic array. Altera Corporation July 2005 RapidIO HyperTransport ...

Page 152

... There is a multiplexer here to select the PLL clock source PLL uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for “low” speed channels, as labeled in the device pin-outs at www.altera.com. 2–138 Stratix Device Handbook, Volume 1 ® ...

Page 153

... There is a multiplexer here to select the PLL clock source PLL uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 Mbps for “high” speed channels and 462 Mbps for “low” speed channels as labeled in the device pin-outs at www.altera.com. Altera Corporation ...

Page 154

... Once operating conditions are reached and the device is configured, Stratix devices operate as specified by the user. For more information, see Hot Socketing in the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2. 2–140 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 ...

Page 155

... If selected, the checksum is automatically loaded to the USERCODE register. In the Settings dialog box in the Assignments menu, click Device & Pin Options, then General, and then turn on the Auto Usercode option. Altera Corporation July 2005 3. Configuration & Testing ® devices provide JTAG BST circuitry that complies with the ® ...

Page 156

... Monitors internal device operation with the SignalTap II embedded logic analyzer. and pins, TDI TDO to be serially shifted and , TDI TDO . TDO and pins, TDI TDO and pins, TDI TDO TM II download low nSTATUS is held low until the Altera Corporation July 2005 ...

Page 157

... EP1S80 0000 Notes to Tables 3–2 and 3–3: (1) The most significant bit (MSB the left. (2) The IDCODE’s least significant bit (LSB) is always 1. Altera Corporation July 2005 Tables 3–2 and Device IDCODE (32 Bits) (1) Manufacturer Identity Part Number (16 Bits) 0010 0000 0000 0001 ...

Page 158

... JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance t t JPSU JPH t JPXZ t JSXZ Min Max Unit 100 Altera Corporation July 2005 ...

Page 159

... JTAG controller. If any of the Stratix, Stratix II, Cyclone, and Cyclone II devices are in the 18th or after they will fail configuration. This does not affect SignalTap II. AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices Jam Programming & Test Language Specification Configuration & Testing , and Cyclone II devices must be ® ...

Page 160

... Stratix Device Handbook, Volume 1 , the POR time is 2 ms. before and during device configuration. If CCIO during configuration, the weak pull- CC ™ MV cable, the V CCIO supply voltage that powers the CCIO supply that CCIO CCIO for the bank containing TDO must Altera Corporation July 2005 ...

Page 161

... For more information on the JRunner software driver, see the JRunner Software Driver: An Embedded Solution to the JTAG Configuration White Paper and the source files on the Altera web site (www.altera.com). Configuration Schemes You can load the configuration data for a Stratix device with one of five configuration schemes (see application ...

Page 162

... Stratix Architecture chapter of the Stratix Device Handbook, Volume 1 for more information on Stratix PLLs. Remote Update Configuration Modes Stratix devices also support remote configuration using an Altera enhanced configuration device (e.g., EPC16, EPC8, and EPC4 devices) with page mode selection. Factory configuration data is stored in the default page of the configuration device ...

Page 163

... Altera Corporation July 2005 Loads a remote update-control register to determine the page address of the new application configuration Determines whether to enable a user watchdog timer for the ...

Page 164

... EPC4 configuration device pages and point to the next page in the configuration device. 3–10 Stratix Device Handbook, Volume 1 Configuration Device (1) Application Configuration Application Configuration Configuration Device Updates Stratix Device with Factory Configuration (to Handle Update) or New Application Configuration Page 7 Page 6 Page 0 Factory Configuration Altera Corporation July 2005 ...

Page 165

... Error Notes to Figure 3–3: (1) Remote update of Application Configuration is controlled by a Nios embedded processor or user logic programmed in the Factory or Application configurations. ( seven pages can be specified allowing up to seven different configuration applications. Altera Corporation July 2005 Notes (1), (2) Power-Up Configuration Error Factory Configuration ...

Page 166

... Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of the best options for mitigating SEU. Detection 3–12 Stratix Device Handbook, Volume 1 shows the transition diagram for local update mode. Power-Up or nCONFIG nCONFIG Application Configuration Configuration Error Configuration Error Factory Configuration nCONFIG Altera Corporation July 2005 ...

Page 167

... CRC circuitry verifies the internal configuration SRAM bits in the FPGA device. For more information on CRC, see AN 357: Error Detection Using CRC in Altera FPGA Devices. Temperature Stratix devices include a diode-connected transistor for use as a temperature sensor in power management. This diode is used with an ...

Page 168

... Series resistance 3–14 Stratix Device Handbook, Volume 1 Stratix Device tempdiodep tempdioden shows the specifications for bias voltage and current of the Parameter Minimum high 80 low 8 – V 0.3 BN Temperature-Sensing Device Typical Maximum Unit μA 100 120 μ 0 Altera Corporation July 2005 ...

Page 169

... Voltage (Across Diode) 0.65 0.60 0.55 0.50 0.45 0.40 –55 Altera Corporation July 2005 Figure 3–6. –30 – Temperature ( C) Stratix Device Handbook, Volume 1 Configuration & Testing 100 μA Bias Current 10 μA Bias Current 70 95 120 ...

Page 170

... Temperature Sensing Diode 3–16 Stratix Device Handbook, Volume 1 Altera Corporation July 2005 ...

Page 171

... Table 4–2. Stratix Device Recommended Operating Conditions (Part Symbol Parameter V Supply voltage for internal CCINT logic and input buffers Altera Corporation January 2006 ® devices are offered in both commercial and industrial grades. and V voltage levels, and input voltage requirements. The CCIO through 4– ...

Page 172

... EP1S80 ground load, no toggling inputs Minimum Maximum Unit 3.00 (3.135) 3.60 (3.465) V 2.375 2.625 V 1.71 1.89 V 1.4 1.6 V –0.5 4 CCIO 0 85 °C –40 100 °C Typical Maximum Unit 114 mA 145 mA 200 mA 277 mA Altera Corporation January 2006 μA μA ...

Page 173

... Low-level output voltage OL Table 4–6. 2.5-V I/O Specifications Symbol Parameter V Output supply voltage CCIO V High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Altera Corporation January 2006 Note (7) (Part Conditions Minimum ( 3 CCIO V = 2.375 V (9) 30 CCIO ( 1. ...

Page 174

... OL Notes to Tables 4–1 through 4–8: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) Conditions beyond those listed in operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns, or overshoot to the voltage shown in for input currents less than 100 mA ...

Page 175

... Figures 4–1 waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V PCML, LVPECL, and HyperTransport technology). Figure 4–1. Receiver Input Waveforms for Differential I/O Standards Single-Ended Waveform Differential Waveform Altera Corporation January 2006 DC & Switching Characteristics Vin (V) Maximum Duty Cycle (%) 4.3 4 ...

Page 176

... V ≤ V < 1.1 V 300 through 10 1.1 V ≤ V ≤ 1.6 V 200 1.1 V ≤ V ≤ 1.6 V 100 through10 ≤ 1.8 V 1.6 V < V 300 through 10 Positive Channel ( Negative Channel ( Ground p − Typical Maximum Unit 3.3 3.465 V 1,000 mV 1,000 mV 1,000 mV 1,000 mV Altera Corporation January 2006 ...

Page 177

... V Output common mode OCM voltage Δ V Change in V between OCM OCM high and low R Receiver differential input L discrete resistor (external to Stratix devices) Altera Corporation January 2006 Conditions Minimum LVDS 100 0.3 V ≤ V ≤ 1 through 10 LVDS 1,600 0.3 V ≤ V ≤ 1 through 10 ...

Page 178

... Conditions Minimum 3.135 300 1 = 100 Ω R 525 L = 100 Ω Typical Maximum Unit 3.3 3.465 V 600 mV 3.465 V 370 500 2.85 3 CCIO Ω Ω Typical Maximum Unit 3.3 3.465 V 1,000 700 970 mV 1.7 1.9 V Ω 100 110 Altera Corporation January 2006 ...

Page 179

... Table 4–14. 3.3-V PCI Specifications Symbol Parameter V Output supply voltage CCIO V High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Altera Corporation January 2006 Conditions Minimum 2.375 300 300 = 100 Ω R 380 L = 100 Ω 100 Ω R 440 L = 100 Ω ...

Page 180

... Conditions Minimum 1.14 0. REF 0. (3) OL Typical Maximum Unit 3 CCIO 0.5 0.35 × CCIO V V 0.1 × CCIO Typical Maximum Unit 1.5 1.65 V 1.0 1. – 0.1 V REF 0.65 V Typical Maximum Unit 1.2 1.26 V 0.8 0. – V REF 0.05 0.4 V Altera Corporation January 2006 ...

Page 181

... TT V High-level DC input voltage IH(DC) V Low-level DC input voltage IL(DC) V High-level AC input voltage IH(AC) V Low-level AC input voltage IL(AC) V High-level output voltage OH V Low-level output voltage OL Altera Corporation January 2006 Conditions Minimum Typical 1.65 0.8 V – 0.04 REF V + REF 0.125 V + REF 0.275 I = –6 ...

Page 182

... V V – 0.35 V REF V V – 0. Maximum Unit 2.5 2.625 0.04 V REF REF 1.25 1. 0.3 V CCIO V – 0.18 V REF V V – 0.35 V REF V V – 0. Maximum Unit 3.3 3 0.05 V REF REF 1.5 1 0.3 V CCIO V – 0.2 V REF V Altera Corporation January 2006 ...

Page 183

... IL V High-level output voltage OH V Low-level output voltage OL Table 4–25. 3.3-V AGP 1× Specifications (Part Symbol Parameter V Output supply voltage CCIO V High-level input voltage IH V Low-level input voltage IL Altera Corporation January 2006 Conditions Minimum I = – Conditions Minimum 3.0 V – 0.05 REF 1 ...

Page 184

... OL Maximum Unit 3.6 V 0.1 × CCIO Maximum Unit 1.5 1.6 V 0.75 0.9 V 0.75 0 – 0.1 V REF V V – 0.2 V REF V 0.4 V Maximum Unit 1.5 1.6 V 0.75 0.9 V 0.75 0 – 0.1 V REF V V – 0.2 V REF V 0.4 V Altera Corporation January 2006 ...

Page 185

... Table 4–30. 1.5-V Differential HSTL Class I & Class II Specifications Symbol Parameter V I/O supply voltage CCIO V (DC) DC input differential DIF voltage V (DC) DC common mode input CM voltage V (AC) AC differential input DIF voltage Altera Corporation January 2006 Conditions Minimum Typical 1.65 0. 0.1 REF –0 0.2 REF ( – – 0.4 OH ...

Page 186

... Typical Maximum Unit 3.3 3.6 1.5 1.65 V – 0.2 REF V – 0.4 REF 10 2.5 V 3.3 V Min Max Min Max 50 70 –50 –70 300 500 –300 –500 0.7 1.7 0.8 2.0 Altera Corporation January 2006 μA Unit μA μA μA μA V ...

Page 187

... Altera Corporation January 2006 Note (5) Minimum . CLK[12:15 CLK10 , and . CLK11 ® offers two ways to calculate power for a design: the Altera web shows the maximum power-up current (I DC & Switching Characteristics Typical Maximum Unit 11.5 pF 8.2 pF 11 ...

Page 188

... The maximum test conditions are for 0° C and typical test conditions are for 40° C. power-up requirement depends on the V CCINT supply reaches approximately 0.75 V. CCINT 4–34. However, the device does ) Requirements Note (1) CCINT Unit Maximum 700 mA 1,200 mA 1,500 mA 1,900 mA 2,300 mA 2,600 mA 3,000 mA Table 4–34. The user-mode CCINT Altera Corporation January 2006 ...

Page 189

... Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worst- case voltage and junction temperature conditions. Table 4–35. Stratix Device Timing Model Status Altera Corporation January 2006 ™ technology and MultiTrack Table 4– ...

Page 190

... MHz 255.55 222.27 188.89 MHz 223.06 194.06 164.93 MHz 233.06 194.06 164.93 MHz 233.06 194.06 164.93 MHz 243.19 211.59 179.82 MHz 223.06 194.06 164.93 MHz 223.06 194.06 164.93 MHz 254.32 221.28 188.00 MHz 237.69 206.82 175.74 MHz Altera Corporation January 2006 ...

Page 191

... This application uses registered inputs and outputs. (4) This application uses registered multiplier input and output stages within the DSP block. (5) This application uses registered multiplier input, pipeline, and output stages within the DSP block. Altera Corporation January 2006 Notes (1), (2) Resources Used ...

Page 192

... Minimum preset pulse width Register minimum clock high or low time. The maximum I/O clock frequency can be calculated by 1/(2 × t Performance may also be affected by I/O timing, use of PLL, and I/O programmable settings. through 4–42 describe the ™ Parameter ). CLKHL Parameter ). CLKHL Altera Corporation January 2006 ...

Page 193

... PD36 t CLR t CLKHL Altera Corporation January 2006 Symbol Input, pipeline, and output register setup time before clock Input, pipeline, and output register hold time after clock Input, pipeline, and output register clock-to-output delay Input Register to DSP Block pipeline register in 9 × 9-bit mode Input Register to DSP Block pipeline register in 18 × ...

Page 194

... Clock enable setup time before clock Clock enable hold time after clock Byte enable setup time before clock Byte enable hold time after clock A port data setup time before clock Parameter Table 4–36 on page 4–20 and as Parameter Altera Corporation January 2006 ...

Page 195

... MRAMDATAAH t MRAMADDRASU t MRAMADDRAH t MRAMDATABSU Altera Corporation January 2006 Symbol A port data hold time after clock A port address setup time before clock A port address hold time after clock B port data setup time before clock B port data hold time after clock B port address setup time before clock ...

Page 196

... The actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in reported by the timing analyzer in the Quartus II software. Minimum clear pulse width. Parameter Table 4–36 on page 4–20 and as Altera Corporation January 2006 ...

Page 197

... LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects. Table 4–43. Routing Delay Internal Timing Microparameter Descriptions (Part Symbol R24 Altera Corporation January 2006 shows the TriMatrix memory waveforms for the M512, M4K WEREH ...

Page 198

... Min Max Min Max 280 280 280 280 80 80 180 180 Parameter -7 -8 Max Min Max 13 135 202 238 527 621 135 135 1400 -7 -8 Min Max Min Max 280 ps 280 180 ps Altera Corporation January 2006 Unit Unit ...

Page 199

... COMBIN2PIN_C t 276 CLR t 260 PRE t 1,000 CLKHL Table 4–47. DSP Block Internal Timing Microparameters (Part Symbol Min INREG2PIPE9 t INREG2PIPE18 Altera Corporation January 2006 -5 -6 Min Max Min Max 80 80 380 380 280 280 280 280 430 430 Max Min Max Min 71 ...

Page 200

... Unit Max Min Max 2,533 2,980 ps 3,667 4,314 ps 4,692 5,520 ps 6,065 7,135 ps 9,481 11,154 ps 676 ps 2,029 Unit Max Min Max 4,387 5,162 ps 4,128 4,860 ps 166 290 ps –95 ps 166 166 166 541 637 ps 4,421 5,203 ps 1,400 ps 255 ps Altera Corporation January 2006 ...

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