EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 156

• Manufacturer Part Number: EP1S30F780I6N
• Description: IC STRATIX FPGA 30K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S30F780I6N

• Number Of Logic Elements/cells: 32470
• Number Of Labs/clbs: 3247
• Total Ram Bits: 3317184
• Number Of I /o: 597
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
3–2
Stratix Device Handbook, Volume 1
Note to
(1)
SAMPLE/PRELOAD 00 0000 0101
EXTEST
BYPASS
USERCODE
IDCODE
HIGHZ
CLAMP
ICR instructions
PULSE_NCONFIG
CONFIG_IO
SignalTap II
instructions
Table 3–1. Stratix JTAG Instructions
JTAG Instruction
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(1)
(1)
Table
(1)
3–1:
11 1111 1111
00 0000 0001
00 0000 1101
00 0000 0000
00 0000 0111
00 0000 0110
00 0000 1011
00 0000 1010
Instruction Code
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
Selects the 32-bit
TDI
out of
Selects the
allowing the
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
Places the 1-bit bypass register between the
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
Used when configuring an Stratix device via the JTAG port with a
MasterBlaster
cable, or when using a Jam File or Jam Byte-Code File via an
embedded processor or JRunner.
Emulates pulsing the
even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, after, or during
configuration. Stops configuration if executed during configuration.
Once issued, the
to reset the configuration device.
device is reconfigured.
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
and
TDO
TDO
.
IDCODE
IDCODE
TM
pins, allowing the
, ByteBlasterMV
CONFIG_IO
USERCODE
register and places it between
nCONFIG
to be serially shifted out of
Description
register and places it between the
instruction will hold
USERCODE
TM
pin low to trigger reconfiguration
nSTATUS
, or ByteBlaster
is held low until the
to be serially shifted
TDI
TDI
TDI
Altera Corporation
TDO
TM
and
and
and
nSTATUS
TDI
II download
.
TDO
TDO
TDO
and
July 2005
pins,
pins,
pins,
TDO
low
,