EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 197

• Manufacturer Part Number: EP1S30F780I6N
• Description: IC STRATIX FPGA 30K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S30F780I6N

• Number Of Logic Elements/cells: 32470
• Number Of Labs/clbs: 3247
• Total Ram Bits: 3317184
• Number Of I /o: 597
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 4–3. Dual-Port RAM Timing Microparameter Waveform
Altera Corporation
January 2006
unreg_data-out
reg_data-out
wraddress
rdaddress
rdclock
data-in
wrclock
wren
rden
doutn-2
an-1
din-1
t
t
DATASU
WERESU
doutn-1
bn
t
DATAH
an
din
Figure 4–3
and M-RAM timing parameters shown in
Internal timing parameters are specified on a speed grade basis
independent of device density.
internal timing microparameters for LEs, IOEs, TriMatrix memory
structures, DSP blocks, and MultiTrack interconnects.
t
t
t
R4
R8
R24
Table 4–43. Routing Delay Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol
t
doutn-1
WEREH
doutn
a0
b0
shows the TriMatrix memory waveforms for the M512, M4K,
Delay for an R4 line with average loading; covers a distance of four
LAB columns.
Delay for an R8 line with average loading; covers a distance of eight
LAB columns.
Delay for an R24 line with average loading; covers a distance of 24
LAB columns.
t
t
DATACO1
WEREH
t
DATACO2
a1
t
RC
doutn
dout0
a2
b1
Tables 4–44
Parameter
t
t
WADDRSU
Stratix Device Handbook, Volume 1
a3
WERESU
dout0
Tables 4–40
DC & Switching Characteristics
through
din4
a4
b2
4–50
through 4–42.
t
WADDRH
show the
din5
a5
b3
din6
a6
4–27