Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 26
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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Z8018x
Family MPU User Manual
11
TOUT. Timer Out (Output, Active High). TOUT is the pulse output from
PRT channel 1. This line is multiplexed with A18 of the address bus.
TXA0, TXA1. Transmit Data 0 and 1 (Outputs, Active High). These
signals are the transmitted data from the ASCI channels. Transmitted data
changes are with respect to the falling edge of the transmit clock.
TXS. Clocked Serial Transmit Data (Output, Active High). This line is
the transmitted data from the CSIO channel.
WAIT. Wait (Input; Active Low). WAIT indicates to the CPU that the
addressed memory or I/O devices are not ready for a data transfer. This
input is used to induce additional clock cycles into the current machine
cycle. The WAIT input is sampled on the falling edge of T2 (and
subsequent Wait States). If the input is sampled Low, then additional Wait
States are inserted until the WAIT input is sampled High, at which time
execution continues.
WR. Write (Output, Active Low, 3-state). WR indicates that the CPU data
bus holds valid data to be stored at the addressed I/O or memory location.
XTAL. Crystal (Input, Active High). Crystal oscillator connection. This
pin must be left open if an external clock is used instead of a crystal. The
oscillator input is not a TTL level (reference DC characteristics).
Multiplexed pins are described in Table 2.
UM005003-0703
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