MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet

IC MICROPROCESSOR 32BIT 184-CQFP

MC68040FE33A

Manufacturer Part Number
MC68040FE33A
Description
IC MICROPROCESSOR 32BIT 184-CQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68040FE33A

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Package
184CQFP
Processor Series
M680xx
Core
CPU32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68040FE33A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
µ MOTOROLA
©MOTOROLA INC., 1990
Revised 1992, 1993
M68040 User’s Manual
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68EC040V
Including the
MC68LC040,
MC68EC040,
MC68040V,
Go to: www.freescale.com
MC68040,
and

MC68040FE33A Summary of contents

Page 1

... Freescale Semiconductor, Inc. µ MOTOROLA M68040 User’s Manual ©MOTOROLA INC., 1990 Revised 1992, 1993 For More Information On This Product, Including the MC68040, MC68040V, MC68LC040, MC68EC040, and MC68EC040V Go to: www.freescale.com ...

Page 2

... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others ...

Page 3

... Freescale Semiconductor, Inc. The complete documentation package for the MC68040, MC68040V, MC68LC040, MC68EC040, and MC68EC040V (collectively called M68040) consists of the M68040UM/AD, M68040 User’s Manual , and the M68000PM/AD, M68000 Family Programmer’s Reference Manual . The M68040 User’s Manual describes the capabilities, operation, and programming of the M68040 32-bit third-generation microprocessors. The M68000 Family Programmer’ ...

Page 4

... Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Number 1.1 Differences ............................................................................................ 1-1 1.1.1 MC68040V and MC68LC040 ............................................................ 1-1 1.1.2 MC68EC040 and MC68EC040V ....................................................... 1-2 1.2 Features ................................................................................................ 1-3 1.3 Extensions to the M68000 Family ......................................................... 1-3 1.4 Functional Blocks .................................................................................. 1-3 1.5 Processing States ................................................................................. 1-5 1.6 Programming Model .............................................................................. 1-5 1 ...

Page 5

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number (Except MC68EC040 and MC68EC040V) 3.1 Memory Management Programming Model .......................................... 3-3 3.1.1 User and Supervisor Root Pointer Registers..................................... 3-3 3.1.2 Translation Control Register .............................................................. 3-4 3.1.3 Transparent Translation Registers .................................................... 3-5 3.1.4 MMU Status Register ........................................................................ 3-6 3 ...

Page 6

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 4.1 Cache Operation ................................................................................... 4-2 4.2 Cache Management.............................................................................. 4-5 4.3 Caching Modes ..................................................................................... 4-6 4.3.1 Cachable Accesses ........................................................................... 4-6 4.3.1.1 Write-Through Mode ...................................................................... 4-6 4.3.1.2 Copyback Mode ............................................................................. 4-6 4.3.2 Cache-Inhibited Accesses ................................................................. 4-7 4.3.3 Special Accesses .............................................................................. 4-7 4.4 Cache Protocol ...

Page 7

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 5.4.2 Transfer in Progress (TIP) ................................................................. 5-8 5.4.3 Transfer Acknowledge (TA) ............................................................... 5-8 5.4.4 Transfer Error Acknowledge (TEA) .................................................... 5-8 5.4.5 Transfer Cache Inhibit (TCI) .............................................................. 5-9 5.4.6 Transfer Burst Inhibit (TBI) ................................................................. 5-9 5.5 Snoop Control Signals........................................................................... 5-9 5.5.1 Snoop Control (SC1, SC0) ...

Page 8

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 6.2.2 HIGHZ ............................................................................................... 6-4 6.2.3 SAMPLE/PRELOAD.......................................................................... 6-4 6.2.4 DRVCTL.T ......................................................................................... 6-4 6.2.5 SHUTDOWN ..................................................................................... 6-5 6.2.6 PRIVATE ........................................................................................... 6-5 6.2.7 DRVCTL.S......................................................................................... 6-5 6.2.8 BYPASS ............................................................................................ 6-6 6.3 Boundary Scan Register ....................................................................... 6-6 6.4 Restrictions ........................................................................................... 6-12 6.5 Disabling The IEEE Standard 1149.1A Operation ................................ 6-13 6 ...

Page 9

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 7.8.2.3 M68040 Synchronous DMA Arbitration .......................................... 7-55 7.8.2.4 M68040 Asynchronous DMA Arbitration ........................................ 7-57 7.9 Bus Snooping Operation ....................................................................... 7-59 7.9.1 Snoop-Inhibited Cycle........................................................................ 7-60 7.9.2 Snoop-Enabled Cycle (No Intervention Required) ............................ 7-61 7.9.3 Snoop Read Cycle (Intervention Required) ....................................... 7-63 7 ...

Page 10

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 8.4.6.5 Write-Back Address and Write-Back Data ..................................... 8-26 8.4.6.6 Push Data ...................................................................................... 8-27 8.4.6.7 Access Error Stack Frame Return From Exception ....................... 8-27 Floating-Point Unit (MC68040 Only) 9.1 Floating-Point Unit Pipeline ................................................................... 9-1 9.2 Floating-Point User Programming Model .............................................. 9-2 9.2.1 Floating-Point Data Registers (FP7– ...

Page 11

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number 9.7.5 Underflow .......................................................................................... 9-33 9.7.5.1 Maskable Exception Conditions ..................................................... 9-34 9.7.5.2 Nonmaskable Exception Conditions .............................................. 9-34 9.7.6 Divide by Zero.................................................................................... 9-36 9.7.7 Inexact Result .................................................................................... 9-36 9.8 Floating-Point State Frames.................................................................. 9-39 10.1 Overview ............................................................................................... 10-3 10.2 Instruction Timing Examples ................................................................. 10-5 10 ...

Page 12

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number Ordering Information and Mechanical Data 12.1 Ordering Information ............................................................................. 12-1 12.2 Pin Assignments ................................................................................... 12-1 12.2.1 MC68040 Pin Grid Array ................................................................... 12-2 12.2.2 MC68LC040 Pin Grid Array............................................................... 12-3 12.2.3 MC68EC040 Pin Grid Array .............................................................. 12-4 12.2.4 MC68040V and MC68EC040V Pin Grid Array .................................. 12-5 12 ...

Page 13

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number B.4 Special Modes Of Operation ................................................................. B-8 B.5 Exception Processing............................................................................ B-10 B.5.1 Unimplemented Floating-Point Instructions and Exceptions ............. B-10 B.5.2 MC68EC040 Stack Frames ............................................................... B-11 B.6 Software Considerations ....................................................................... B-12 B.7 MC68EC040 Electrical Characteristics ................................................. B-12 B.7.1 Maximum Ratings .............................................................................. B-12 B ...

Page 14

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Number C.7 MC68040V and MC68EC040V Electrical Characteristics..................... C-19 C.7.1 Maximum Ratings .............................................................................. C-19 C.7.2 Thermal Characteristics .................................................................... C-19 C.7.3 DC Electrical Specifications .............................................................. C-20 C.7.4 Power Dissipation.............................................................................. C-20 C.7.5 Clock AC Timing Specifications ........................................................ C-21 C.7.6 Output AC Timing Specifications ....................................................... C-22 C ...

Page 15

... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure Number 1-1 Block Diagram .............................................................................................. 1-4 1-2 Programming Model ..................................................................................... 1-7 2-1 Integer Unit Pipeline ..................................................................................... 2-2 2-2 Write-Back Cycle Block Diagram ................................................................. 2-3 2-3 Integer Unit User Programming Model......................................................... 2-4 2-4 Integer Unit Supervisor Programming Model ............................................... 2-6 2-5 Status Register ...

Page 16

... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number 4-5 Instruction-Cache Line State Diagram ......................................................... 4-14 4-6 Data-Cache Line State Diagram .................................................................. 4-16 5-1 Functional Signal Groups ............................................................................. 5-4 6-1 M68040 Test Logic Block Diagram .............................................................. 6-2 6-2 Bypass Register ........................................................................................... 6-6 6-3 Output Latch Cell (O.Latch) ......................................................................... 6-7 6-4 Input Pin Cell (I ...

Page 17

... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number 7-26 Word Write Access Terminated with TEA Timing ........................................ 7-39 7-27 Line Read Access Terminated with TEA Timing .......................................... 7-40 7-28 Retry Read Transfer Timing ......................................................................... 7-41 7-29 Retry Operation on Line Write ...................................................................... 7-42 7-30 M68040 Internal Interpretation State Diagram and External Bus Arbiter Circuit ...

Page 18

... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number 9-9 Format of Denormalized Operand in State Frame ....................................... 9-24 9-10 MC68040 Floating-Point State Frames ........................................................ 9-40 9-11 Mapping of Command Bits for CMDREG3B Field ....................................... 9-42 10-1 Simple Instruction Timing Example .............................................................. 10-5 10-2 Instruction Overlap with Multiple Clocks ...................................................... 10-6 10-3 Interlocked Stages ...

Page 19

... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS (Continued) Figure Number B-10 Snoop Hit Timing.......................................................................................... B-19 B-11 Snoop Miss Timing....................................................................................... B-20 B-12 Other Signal Timing ..................................................................................... B-21 C-1 MC68040V and MC68EC040V Functional Signal Groups ........................... C-3 C-2 MC68040V and MC68EC040V Initial Power-On Reset Timing ................... C-8 C-3 MC68040V and MC68EC040V Normal Reset Timing ...

Page 20

... Freescale Semiconductor, Inc. Table Number 1-1 M68040 Data Formats ................................................................................. 1-9 1-2 Effective Addressing Modes ........................................................................ 1-10 1-3 Notational Conventions ................................................................................ 1-11 1-4 Instruction Set Summary.............................................................................. 1-14 3-1 Updating U-Bit and M-Bit for Page Descriptors............................................ 3-22 3-2 SFC and DFC Values................................................................................... 3-22 4-1 Snoop Control Encoding .............................................................................. 4-9 4-2 TLNx Encoding ...

Page 21

... Freescale Semiconductor, Inc. LIST OF TABLES (Continued) Table Number 8-5 Write-Back Data Alignment .......................................................................... 8-27 8-6 Access Error Stack Frame Combinations .................................................... 8-31 9-1 Floating-Point Control Register Encodings .................................................. 9-3 9-2 MC68040 FPU Data Formats and Data Types ............................................ 9-7 9-3 Single-Precision Real Format Summary ...................................................... 9-8 9-4 Double-Precision Real Format Summary ...

Page 22

... Freescale Semiconductor, Inc. SECTION 1 INTRODUCTION The MC68040, MC68040V, MC68LC040, MC68EC040, and MC68EC040V (collectively called M68040) are Motorola’s third generation of M68000-compatible, high-performance, 32-bit microprocessors. All five devices are virtual memory microprocessors employing multiple concurrent execution units and a highly integrated architecture that provides very high performance in a monolithic HCMOS device ...

Page 23

... Freescale Semiconductor, Inc. • The DLE pin name has been changed to JS0 on both the MC68040V and MC68LC040. In addition, the MC68040V contains three new pins, system clock disable (SCD ), low frequency operation (LFO), and loss of clock (LOC ). • The MC68040V and MC68LC040 do not implement the data latch enable (DLE), multiplexed, or output buffer impedance selection modes of operation ...

Page 24

... Freescale Semiconductor, Inc. 1.2 FEATURES The main features of the M68040 are as follows: • 6-Stage Pipeline, MC68030-Compatible IU • MC68881/MC68882-Compatible FPU • Independent Instruction and Data MMUs • Simultaneously Accessible, 4-Kbyte Physical Instruction Cache and 4-Kbyte Physical Data Cache • Low-Latency Bus Accesses for Reduced Cache Miss Penalty • ...

Page 25

... Freescale Semiconductor, Inc. more common case of the branch taken, and both execution paths of the branch are fetched and decoded to minimize refilling of the instruction pipeline. INSTRUCTION FETCH CONVERT DECODE EA CALCULATE EXECUTE EA FETCH EXECUTE WRITE- BACK WRITE- BACK FLOATING- INTEGER UNIT POINT UNIT To improve memory management, the M68040 includes separate, independent paged MMUs for instruction and data accesses ...

Page 26

... Freescale Semiconductor, Inc. masters in the system. Both caches are organized as four-way set associative with 64 sets of four lines. Each line contains four long words for a storage capability of 4 Kbytes for each cache (8 Kbytes total). Each cache and corresponding MMU is allocated separate internal address and data buses, allowing simultaneous access to both. The data cache provides write-through or copyback write modes that can be configured on a page-by-page basis ...

Page 27

... Freescale Semiconductor, Inc. uses. The IU identifies a logical address by accessing either the supervisor or user address space, maintaining the differentiation between supervisor and user modes. The MMUs use the indicated privilege mode to control and translate memory accesses, protecting supervisor code, data, and resources from user program accesses. Refer to Appendix B MC68EC040 for details concerning the MC68EC040 address translation ...

Page 28

... Freescale Semiconductor, Inc. Only system programmers can use the supervisor programming model to implement operating system functions, I/O control, and memory management subsystems. This supervisor/user distinction in the M68000 family architecture allows for the writing of application software that executes in the user mode and migrates to the MC68040 from any M68000 family platform without modification ...

Page 29

... Freescale Semiconductor, Inc. The user programming model includes eight data registers, seven address registers, and a stack pointer register. The address registers and stack pointer can be used as base address registers or software stack pointers, and any of the 16 registers can be used as index registers. Two control registers are available in the user mode—the program ...

Page 30

... Freescale Semiconductor, Inc. 1.7 DATA FORMAT SUMMARY The M68040 supports the basic data formats of the M68000 family. Some data formats apply only to the IU, some only to the FPU, and some to both. In addition, the instruction set supports operations on other data formats such as memory addresses. ...

Page 31

... Freescale Semiconductor, Inc. applications and high-level languages. The program counter indirect mode also has indexing and offset capabilities. This addressing mode is typically required to support position-independent software. Besides these addressing modes, the M68040 provides index sizing and scaling features. An instruction’s addressing mode can specify the value of an operand, a register containing the operand, or how to derive the effective address of an operand in memory ...

Page 32

... Freescale Semiconductor, Inc. 1.9 NOTATIONAL CONVENTIONS Table 1-3 lists the notation conventions used throughout this manual unless otherwise specified. Table 1-3. Notational Conventions Single- And Double-Operand Operations + Arithmetic addition or postincrement indicator. – Arithmetic subtraction or predecrement indicator. Arithmetic multiplication. Arithmetic division or conjunction symbol. ...

Page 33

... Freescale Semiconductor, Inc. Table 1-3. Notational Conventions (Continued) + inf Positive Infinity <fmt> Operand Data Format: Byte (B), Word (W), Long (L), Single (S), Double (D), Extended (X), or Packed (P Specifies a signed integer data type (twos complement) of byte, word, or long word. D Double-precision real data format (64 bits twos complement signed integer (–64 to +17) specifying a number’s format to be stored in the packed decimal format ...

Page 34

... Freescale Semiconductor, Inc. Table 1-3. Notational Conventions (Concluded) * General Case. C Carry Bit in CCR cc Condition Codes from CCR FC Function Code N Negative Bit in CCR U Undefined, Reserved for Motorola Use. V Overflow Bit in CCR X Extend Bit in CCR Z Zero Bit in CCR — Not Affected or Applicable. ISP ...

Page 35

... Freescale Semiconductor, Inc. Table 1-4. Instruction Set Summary Opcode ABCD BCD Source + BCD Destination + X ø Destination ADD Source + Destination ø Destination ADDA Source + Destination ø Destination ADDI Immediate Data + Destination ø Destination ADDQ Immediate Data + Destination ø Destination ADDX Source + Destination + X ø Destination ...

Page 36

... Freescale Semiconductor, Inc. Table 1-4. Instruction Set Summary (Continued) Opcode BTST –(bit number of Destination) ø Z; CAS CAS Destination – Compare Operand ø cc Update Operand ø Destination else Destination ø Compare Operand CAS2 CAS2 Destination 1 – Compare 1 ø cc Destination 2 – Compare ø cc; ...

Page 37

... Freescale Semiconductor, Inc. Table 1-4. Instruction Set Summary (Continued) Opcode EXG Rx ł ø Ry EXT Destination Sign – Extended ø Destination EXTB FABS 2 Absolute Value of Source ø FPn FADD 2 Source + FPn ø FPn FBcc 2 If condition true then ø PC FCMP 2 FPn – Source ...

Page 38

... Freescale Semiconductor, Inc. Table 1-4. Instruction Set Summary (Continued) Opcode FNEG 2 –(Source) ø FPn FNOP 2 None FRESTORE supervisor state then FPU State Frame ø Internal State else TRAP FSAVE supervisor state then FPU Internal State ø State Frame else TRAP ...

Page 39

... Freescale Semiconductor, Inc. Table 1-4. Instruction Set Summary (Continued) Opcode LPSTOP 6 If supervisor state immediate data ø ø broadcast cycle STOP else TRAP LSL, LSR Destination Shifted by count ø Destination MOVE Source ø Destination MOVEA Source ø Destination MOVE CCR ø Destination ...

Page 40

... Freescale Semiconductor, Inc. Table 1-4. Instruction Set Summary (Continued) Opcode NOP None NOT ~ Destination ø Destination OR Source V Destination ø Destination ORI Immediate Data V Destination ø Destination ORI to CCR Source V CCR ø CCR ORI supervisor state then Source V SR ø SR else TRAP PACK Source (Unpacked BCD) + adjustment ø ...

Page 41

... Freescale Semiconductor, Inc. Table 1-4. Instruction Set Summary (Concluded) Opcode SUBA Destination – Source ø Destination SUBI Destination – Immediate Data ø Destination SUBQ Destination – Immediate Data ø Destination SUBX Destination – Source – X ø Destination SWAP Register 31–16 ¯ ø Register 15–0 TAS Destination Tested ø ...

Page 42

... Freescale Semiconductor, Inc. SECTION 2 INTEGER UNIT This section describes the organization of the M68040 integer unit (IU) and presents a brief description of the associated registers. Refer to Section 3 Memory Management Unit (Except MC68EC040 and MC68EC040V) for details concerning the memory management unit (MMU) programming model, and to Section 9 Floating-Point Unit (MC68040 Only) for details concerning the floating-point unit (FPU) programming model ...

Page 43

... Freescale Semiconductor, Inc. SHADOW SHADOW TO FPU Figure 2-1. Integer Unit Pipeline An instruction stream is fetched from the instruction memory unit and decoded on an instruction-by-instruction basis in the decode stage. Multiple instructions are fetched to keep the pipeline stages full so that the pipeline will not stall. ...

Page 44

... Freescale Semiconductor, Inc. effective address. Also, some instructions access multiple memory operands and initiate fetches for each operand. The instruction finishes execution in the execute stage. Instructions with write-back operands to memory generate pending write accesses that are passed to the write-back stage. The write occurs to the data memory unit not busy. If the following instruction, which is in the < ...

Page 45

... Freescale Semiconductor, Inc. 2.2 INTEGER UNIT REGISTER DESCRIPTION The following paragraphs describe the IU registers in the user and supervisor programming models. Refer to Section 3 Memory Management Unit (Except MC68EC040 and MC68EC040V) for details on the MMU programming model and Section 9 Floating-Point Unit (MC68040 Only) for details on the FPU programming model ...

Page 46

... Freescale Semiconductor, Inc. 2.2.1.3 SYSTEM STACK POINTER (A7 used as a hardware stack pointer during stacking for subroutine calls and exception handling. The register designation A7 refers to three different uses of the register: the user stack pointer (USP) (A7) in the user programming model and either the interrupt stack pointer (ISP) or master stack pointer (MSP) (A7' or A7" ...

Page 47

... Freescale Semiconductor, Inc Figure 2-4. Integer Unit Supervisor Programming Model The supervisor programming model consists of the registers available to the user as well as the following control registers: • Two 32-Bit Supervisor Stack Pointers (ISP, MSP) • 16-Bit Status Register (SR) • 32-Bit Vector Base Register (VBR) • ...

Page 48

... Freescale Semiconductor, Inc. procedure separates task-related supervisor activity from asynchronous, I/O-related supervisor tasks that can only be coincidental to the currently executing task. The MSP can separately maintain task control information for each currently executing user task, and the software updates the MSP when a task switch is performed, providing an efficient means for transferring task-related stack items ...

Page 49

... Freescale Semiconductor, Inc. 2.2.2.5 CACHE CONTROL REGISTER. The CACR contains two enable bits that allow the instruction and data caches to be independently enabled or disabled. Setting an enable bit enables the associated cache without affecting the state of any lines within the cache. A hardware reset clears the CACR, disabling both caches. ...

Page 50

... Freescale Semiconductor, Inc. SECTION 3 MEMORY MANAGEMENT UNIT (EXCEPT MC68EC040 AND MC68EC040V) This section does not apply to the MC68EC040 and MC68EC040V. Refer to Appendix B MC68EC040 for details. All references to M68040 in this section only, refer to the MC68040, MC68040V, and MC68LC040. The M68040 supports a demand-paged virtual memory environment. Demand means that programs request memory accesses through logical addresses, and paged means that memory is divided into blocks of equal size, called page frames ...

Page 51

... Freescale Semiconductor, Inc. indexing into the on-chip instruction and data caches. The MMU MDIS signal dynamically disables address translation for emulation and diagnostic support. Figure 3-1 illustrates the MMUs contained in the two memory units, one for instructions (supporting instruction prefetches) and one for data (supporting all other accesses). Each unit contains an MMU, main cache, and snoop controller ...

Page 52

... Freescale Semiconductor, Inc. logical address bits. If the translation is resident, the MMU provides the physical address to the cache controller, which determines if the instruction or data being accessed is cached. The cache controller uses the lower address bits to index into memory. An external bus cycle is performed only when explicitly requested by the cache controller. ...

Page 53

... Freescale Semiconductor, Inc address loaded into the URP or the SRP must be zero. Transfers of data to and from these 32-bit registers are long-word transfers. 31 USER ROOT POINTER SUPERVISOR ROOT POINTER Figure 3-3. URP and SRP Register Formats 3.1.2 Translation Control Register The 16-bit TCR contains two control bits to enable paged address translation and to select page size ...

Page 54

... Freescale Semiconductor, Inc. 3.1.3 Transparent Translation Registers The data transparent translation registers (DTTR0 and DTTR1) and instruction transparent translation registers (ITTR0 and ITTR1) are 32-bit registers that define blocks of logical address space. The TTRs operate independently of the E-bit in the TCR and the state of the MDIS signal ...

Page 55

... Freescale Semiconductor, Inc. CM—Cache Mode This field selects the cache mode and access serialization as follows Cachable, Write-through 01 = Cachable, Copyback 10 = Noncachable, Serialized 11 = Noncachable Section 4 Instruction and Data Caches provides detailed information on caching modes, and Section 7 Bus Operation provides information on serialization. W—Write Protect This bit indicates if the transparent block is write protected ...

Page 56

... Freescale Semiconductor, Inc. S—Supervisor Protection This bit is set if the S-bit in the page descriptor is set. Setting this bit does not indicate that a violation has occurred. CM—Cache Mode This 2-bit field is copied from the CM bits in the page descriptor. M—Modified This bit is set if the M-bit is set in the page descriptor associated with the address. ...

Page 57

... Freescale Semiconductor, Inc. the logical addresses of the currently executing process. Portions of translation tables can be dynamically allocated as the process requires additional memory. ROOT POINTER Figure 3-7. Translation Table Structure The current privilege mode determines the use of the URP or SRP for translation of the access. The root pointer contains the base address of the translation table’ ...

Page 58

... Freescale Semiconductor, Inc BITS 7 BITS ROOT INDEX FIELD POINTER INDEX FIELD (RI) Figure 3-8. Logical Address Format The seven bits of a logical address PI field are multiplied by 4 (shifted to the left by two bits) and concatenated with the fetched root-level descriptor’s upper 23 bits to produce the physical address of the pointer-level table descriptor ...

Page 59

... Freescale Semiconductor, Inc. 'INVALID' 'INVALID' 'INVALID' OTHERWISE CREATE ATC ENTRY WITH R-BIT CLEAR EXIT TABLE SEARCH ABBREVIATIONS: PFA - PAGE FRAME ADDRESS DF DESCRIPTOR FIELD WP - ACCUMULATED WRITE- PROTECTION STATUS ASSIGNMENT OPERATOR Figure 3-9. Detailed Flowchart of Table Search Operation 3-10 For More Information On This Product, ...

Page 60

... Freescale Semiconductor, Inc. TYPE = 'PAGE' OR 'POINTER' FETCH DESCRIPTOR (INDEX*4) (INDEX = RI, PI, OR PGI) IF SCHEDULED, EXECUTE WRITE ACCESS (U PREVIOUS DESCRIPTOR (SEE NOTE) OTHERWISE CREATE ATC ENTRY WITH R-BIT CLEAR EXIT TABLE SEARCH 'INVALID' 'RESIDENT' RETURN SCHEDULE WRITE ACCESS U 1 (SEE NOTE) RETURN DUE TO ACCESS PIPELINING, A POINTER ...

Page 61

... Freescale Semiconductor, Inc. Motorola highly recommends that the translation tables be placed in cache-inhibited memory space. Motorola also highly recommends table descriptors must not be left in states that are incoherent to the processor. Future processors may treat these recommendations as mandatory. The following paragraphs apply only to M68040 systems that cannot meet these recommendations ...

Page 62

... Freescale Semiconductor, Inc. 31 POINTER TABLE ADDRESS ROOT TABLE DESCRIPTOR (ROOT LEVEL) 31 PAGE TABLE ADDRESS 4K POINTER TABLE DESCRIPTOR (POINTER LEVEL) 31 PAGE TABLE ADDRESS 8K POINTER TABLE DESCRIPTOR (POINTER LEVEL) Figure 3-11. Table Descriptor Formats 3.2.2.2 PAGE DESCRIPTORS. Figure 3-12 illustrates the page descriptors for both 4-Kbyte and 8-Kbyte page sizes ...

Page 63

... Freescale Semiconductor, Inc. Descriptor Address This 30-bit field, which contains the physical address of a page descriptor, is only used in indirect descriptors. G—Global When this bit is set, it indicates the entry is global. PFLUSH instruction variants that specify nonglobal entries do not invalidate global entries, even when all other selection criteria are satisfied ...

Page 64

... Freescale Semiconductor, Inc. Page Table Address This field contains the physical base address of a table of page descriptors. The low- order bits of the address required to index into the page table are supplied by the logical address. U—Used The processor automatically sets this bit when a descriptor is accessed in which the U-bit is clear ...

Page 65

... Freescale Semiconductor, Inc. 3.2.3 Translation Table Example Figure 3-13 illustrates an access example to the logical address $76543210 while in the supervisor mode with an 8-Kbyte memory page size. The RI field of the logical address, $3B, is mapped into bits 8–2 of the SRP value to select a 32-bit root table descriptor at a root-level table. The selected root table descriptor points to the base of a pointer-level table, and the PI field of the logical address, $15, is mapped into bits 8– ...

Page 66

... Freescale Semiconductor, Inc. ROOT INDEX $76543210 = $3B TABLE ENTRY # = ADDRESS OFFSET = $EC SUPERVISOR SRP MODE Figure 3-13. Example Translation Table Using the indirection capability, single entries or entire tables can be shared between multiple tasks. Figure 3-14 illustrates two tasks sharing a page using indirect descriptors. ...

Page 67

... Freescale Semiconductor, Inc. ROOT INDEX $76543210 = $3B TABLE ENTRY # = $EC ADDRESS OFFSET = ROOT POINTER TASK A ROOT POINTER TASK B Figure 3-14. Translation Table Using Indirect Descriptors 3.2.4.2 TABLE SHARING BETWEEN TASKS. More than one task can share a pointer- or page-level table by placing a pointer to a shared table in the address translation tables. ...

Page 68

... Freescale Semiconductor, Inc. ROOT INDEX $76543210 = $3B TABLE ENTRY # = $EC ADDRESS OFFSET = ROOT POINTER TASK A ROOT POINTER TASK B * Page frame address shared by task A and B; write protected from task A. Figure 3-15. Translation Table Using Shared Tables 3.2.4.3 TABLE PAGING. The entire translation table for an active task need not be resident in main memory ...

Page 69

... Freescale Semiconductor, Inc. interpretation allows the operating system to store system-defined information in the remaining bits. Information typically stored includes the reason for the invalid encoding (tables paged out, region unallocated, etc.) and possibly the disk address for nonresident tables. Figure 3-16 illustrates an address translation table in which only a single page table (table $15) is resident ...

Page 70

... Freescale Semiconductor, Inc. 3.2.4.4 DYNAMICALLY ALLOCATED TABLES. Similar to paged tables, a complete translation table need not exist for an active task. The operating system can dynamically allocate the translation table based on requests for access to particular areas demand paging difficult, if not impossible, to predict the areas of memory that a task uses over any extended period ...

Page 71

... Freescale Semiconductor, Inc. Table 3-1. Updating U-Bit and M-Bit for Page Descriptors Previous Status U-Bit M-Bit WP Bit NOTE: WP indicates the accumulated write-protect status. An alternate address space access is a special case that is immediately used as a physical address without translation. Because the M68040 implements a merged instruction and data space, the integer unit translates MOVES accesses to instruction address spaces (SFC/DFC = $6 or $2) into data references (SFC/DFC = $5 or $1) ...

Page 72

... Freescale Semiconductor, Inc. 3.2.6 Address Translation Protection The M68040 MMUs provide separate translation tables for supervisor and user address spaces. The translation tables contain both mapping and protection information. Each table and page descriptor includes a write-protect (W) bit that can be set to provide write protection at any level ...

Page 73

... Freescale Semiconductor, Inc. FOR TASK 'A' URP FOR TASK 'A' FOR TASK 'B' URP FOR TASK 'B' POINTER COMMON SRP Figure 3-17. Translation Table Structure for Two Tasks 3.2.6.3 WRITE PROTECT. The M68040 provides write protection independent of other protection mechanisms. All table and page descriptors contain W-bits to protect areas of memory from write accesses of any kind, including supervisor writes ...

Page 74

... Freescale Semiconductor, Inc. PRIVILEGE SRP MODE URP URP & SRP POINT TO SAME A LEVEL TABLE NOTE Don’t care. Figure 3-19. Translation Table Using S-Bit and W-Bit To Set Protection MOTOROLA For More Information On This Product ROOT-LEVEL POINTER-LEVEL TABLE TABLE M68040 USER'S MANUAL Go to: www ...

Page 75

... Freescale Semiconductor, Inc. 3.3 ADDRESS TRANSLATION CACHES The ATCs in the MMUs are four-way set-associative caches that each store 64 logical-to- physical address translations and associated page information similar in form to the corresponding page descriptors in memory. The purpose of the ATC is to provide a fast mechanism for address translation by avoiding the overhead associated with a table search of the logical-to-physical mapping of recently used logical addresses ...

Page 76

... Freescale Semiconductor, Inc. Each ATC entry consists of a physical address, attribute information from a corresponding page descriptor, and a tag that contains a logical address and status information. Figure 3-21, which illustrates the entry and tag fields, is followed by field definitions listed in alphabetical order ENTRY ...

Page 77

... Freescale Semiconductor, Inc. procedure ensures that the first write operation to a page sets the M-bit in both the ATC and the page descriptor in the translation tables, even when a previous read operation to the page had created an entry for that page in the ATC with the M-bit clear. ...

Page 78

... Freescale Semiconductor, Inc. translation in the ATC and provides the physical address for the access, allowing the memory unit to retry the original access. There are some variations in the logical-to-physical mapping because of the two page sizes. If the page size is 4 Kbytes, then logical address bit 12 is used to access the ATC's memory, the tag comparators use bit 16, and physical address bit ATC output ...

Page 79

... Freescale Semiconductor, Inc. By appropriately configuring a TTR, flexible transparent mappings can be specified (refer to 3.1.3 Transparent Translation Registers for field identification). For instance, to transparently translate the user address space, the S-field is set to $0, and the logical address mask is set to $FF in both an instruction and data TTR. To transparently translate supervisor accesses of addresses $00000000– ...

Page 80

... Freescale Semiconductor, Inc. instruction, and the stacked FA points to the first longword in the missing page. When an ATC access error occurs while prefetching the next instruction on the non-existant page after a change of flow instruction, the exception should be cleared by execution of the new instruction flow. Either avoid this scenario, or have a dummy resident page following the exceptional instruction ...

Page 81

... Freescale Semiconductor, Inc. ATC MISS ( [( AND (WRITE OR RMW CYCLE)] ABORT CYCLE TAKE ACCESS ERROR EXCEPTION ( AND (WRITE OR RMW CYCLE) ABORT CYCLE TABLE SEARCH OPERATION * Refers to either instruction or data transparent translation register. Figure 3-22. Address Translation Flowchart 3-32 For More Information On This Product, ...

Page 82

... Freescale Semiconductor, Inc. 3.7 MMU INSTRUCTIONS The M68040 instruction set includes three privileged instructions that perform MMU operations. The following paragraphs briefly describe each of these instructions. For detailed descriptions of these instructions, refer to M68000PR/AD, M68000 Family Programmer's Reference Manual . 3.7.1 MOVEC The MOVEC instruction transfers data between an integer data register, or memory location, and any of the M68040 control and status registers ...

Page 83

... Freescale Semiconductor, Inc. MC68030 and MC68851 cause F-line unimplemented instruction exceptions if executed in either supervisor or user mode by the M68040. 3.7.4 Register Programming Considerations If the entries in the ATCs are no longer valid when a reset operation occurs (as is normally expected), an explicit flush operation must be specified by the system software. The assertion of RSTI disables translation by clearing the E-bits of the TCR, DTTRx, and ITTRx, but it does not flush the ATCs ...

Page 84

... Freescale Semiconductor, Inc AND (USER ACCESS INDICATED IN STACK FRAME) OTHERWISE BRANCH TO "SUPERVISOR OTHERWISE WRITE OR RMW ACCESS INDICATED IN STACK NOT MMU * Refers to either instruction or data transparent translation register. Figure 3-23. MMU Status Interpretation MOTOROLA For More Information On This Product, PTEST (An BRANCH TO "BUS ERROR DURING TABLE SEARCH" ...

Page 85

... Freescale Semiconductor, Inc. SECTION 4 INSTRUCTION AND DATA CACHES Ignore all references to the memory management unit (MMU) when reading for the MC68EC040 and MC68EC040V. The functionality of the MC68040 transparent translation registers has been changed in the MC68EC040 and MC68EC040V to the access control registers. Refer to Appendix B MC68EC040 for details ...

Page 86

... Freescale Semiconductor, Inc. memory is always updated through an external bus access after updating the cache, keeping memory and cached data consistent. INSTRUCTION FETCH CONVERT DECODE EA CALCULATE EXECUTE EA FETCH EXECUTE WRITE- BACK WRITEBACK FLOATING- INTEGER POINT UNIT UNIT Figure 4-1. Overview of Internal Caches 4 ...

Page 87

... Freescale Semiconductor, Inc. TAG V TAG V LW3 TAG — 22-Bit Physical Address Tag V — Line VALID Bit LW — Long Word n (32-Bit) Data Entry Dn — DIRTY Bit for Long Word n Figure 4-2. Cache Line Formats The cache stores an entire line, providing validity on a line-by-line basis. Only burst mode accesses that successfully read four long words can be cached ...

Page 88

... Freescale Semiconductor, Inc. LOGICAL ADDRESS 31 PAGE FRAME S SUPERVISOR BIT LA31–LA12 PA11–PA10 ADDRESS PA31–PA12 TRANSLATION CACHE Figure 4-3. Caching Operation Both caches contain circuitry to automatically determine which cache line in a set to use for a new line. The cache controller locates the first invalid line and uses it invalid lines exist, then a pseudo-random replacement algorithm is used to select a valid line, replacing it with the new line ...

Page 89

... Freescale Semiconductor, Inc. 4.2 CACHE MANAGEMENT Using the MOVEC instruction, the caches are individually enabled to access the 32-bit cache control register (CACR) illustrated in Figure 4-4. The CACR contains two enable bits that allow the instruction and data caches to be independently enabled or disabled. ...

Page 90

... Freescale Semiconductor, Inc. entire cache, and can select one or both caches for the operation. For line and page operations, a physical address in an address register specifies the memory address. 4.3 CACHING MODES Every IU access to the cache has an associated caching mode that determines how the cache handles the access ...

Page 91

... Freescale Semiconductor, Inc. 4.3.2 Cache-Inhibited Accesses Address space regions containing targets such as I/O devices and shared data structures in multiprocessing systems can be designated cache inhibited page descriptor’s CM field indicates nonserialized or serialized, then the access is cache inhibited. The caching operation is identical for both cache-inhibited modes. If the CM field of a matching address indicates either nonserialized or serialized modes, the cache controller bypasses the cache and performs an external bus transfer ...

Page 92

... Freescale Semiconductor, Inc. only if the bus transfer is marked as snoopable on the bus. The protocols described in the following paragraphs assume that the data is cachable (i.e., write-through and copyback). 4.4.1 Read Miss A processor read that misses in the cache causes the cache controller to request a bus transaction that reads the needed line from memory and supplies the required data to the IU ...

Page 93

... Freescale Semiconductor, Inc. avoided by pushing cache lines when a page descriptor is changed and ensuring that alternate bus masters indicate the appropriate snoop operation for writes to corresponding pages (i.e., mark invalid for write-through pages and sink data for copyback pages). If the access is copyback, the cache controller updates the cache line and sets the D-bit for of the appropriate long words in the cache line ...

Page 94

... Freescale Semiconductor, Inc. implementing multiple MC68040s as bus masters, shared data should be stored in write- through pages. This procedure allows each processor to cache shared data for read access while forcing a processor write to shared data to appear as an external write to memory, which the other processors can snoop. ...

Page 95

... Freescale Semiconductor, Inc. 4.6 MEMORY ACCESSES FOR CACHE MAINTENANCE The cache controller in each memory unit performs all maintenance activities that supply data from the cache to the execution units. The activities include requesting accesses to the bus interface unit for reading new cache lines and writing dirty cache lines to memory. ...

Page 96

... Freescale Semiconductor, Inc. access in which the operand spans two line entries, the first cycle corresponds to the line entry containing the portion of the operand at the lower address. The cache controller temporarily stores the data from each cycle in a line read buffer, where it is immediately available to the IU misaligned access spans two entries in the line, the second portion of the operand is available to the IU as soon as the second memory cycle completes ...

Page 97

... Freescale Semiconductor, Inc. read resulting from a write miss in copyback mode is cache inhibited, the write access misses in the cache and writes through to memory. 4.6.2 Cache Pushes When the cache controller selects a dirty data cache line for replacement, memory must be updated with the dirty data before the line is replaced. This occurs when a CPUSH instruction execution explicitly selects the cache and when a cache inhibit access hits in the cache. To reduce the requested data’ ...

Page 98

... Freescale Semiconductor, Inc. 4.7.1 Instruction Cache The IU uses the instruction cache to store instruction prefetches as it requests them. Instruction prefetches are normally requested from sequential memory locations except when a change of program flow occurs (e.g., a branch taken) or when an instruction that can modify the status register (SR) is executed, in which case the instruction pipe is automatically flushed and refilled ...

Page 99

... Freescale Semiconductor, Inc. Table 4-3. Instruction-Cache Line State Transitions Cache Operation CPU Read Miss CPU Read Hit Cache Invalidate or Push (CINV or CPUSH) Alternate Master Read Hit (Snoop Control = 01 — Leave Dirty) Alternate Master Read Hit (Snoop Control = 10 — Invalidate) Alternate Master Write Hit (Snoop Control = 01 — ...

Page 100

... Freescale Semiconductor, Inc. I4—CPU WRITE MISS/WT I7—CINV I8—CPUSH INVALID I3—CPU WRITE MISS/CB D7—CINV D8—CPUSH D10—SNOOP READ HIT/INVALIDATE D11—SNOOP WRITE HIT/ INVALIDATE D13—SNOOP WRITE HIT/SINK DATA & SIZE = LINE ABBREVIATIONS: WT—WRITE-THROUGH MODE CB—COPYBACK MODE SNOOP OPERATION INDICATES: READ OR WRITE / SNOOP CONTROL ENCODING Figure 4-6 ...

Page 101

... Freescale Semiconductor, Inc. Table 4-4. Data-Cache Line State Transitions Cache Operation CPU Read Miss I1 Read line from memory; supply data to CPU and update cache valid state. CPU Read Hit I2 Not Possible CPU Write Miss I3 Read line from (Copyback) memory into cache; ...

Page 102

... Freescale Semiconductor, Inc. Table 4-4. Data-Cache Line State Transitions (Continued) Cache Operation Alternate Master Read Hit I10 Not Possible (Snoop Control = 10 — Invalidate) Alternate Master Write Hit I11 Not Possible (Snoop Control = 10 —Invalidate) Alternate Master Write Hit I12 Not Possible (Snoop Control = 01 — ...

Page 103

... Freescale Semiconductor, Inc. SECTION 5 SIGNAL DESCRIPTION This section contains brief descriptions of the input and output signals in their functional groups (see Figure 5-1). Each signal’s function is briefly explained, referencing other sections that contain detailed information about the signal and related operations. Table 5-1 lists the signal names, mnemonics, and functional descriptions of the input and output signals for the M68040 ...

Page 104

... Freescale Semiconductor, Inc. Signal Name Mnemonic Address Bus A31–A0 Data Bus D31–D0 Transfer Type TT1,TT0 Transfer Modifier TM2–TM0 Transfer Line Number TLN1,TLN0 User-Programmable UPA1,UPA0 User-defined signals, controlled by the corresponding user attribute bits from Attributes Read/Write R/W Transfer Size ...

Page 105

... Freescale Semiconductor, Inc. Table 5-1. Signal Index (Continued) Signal Name Mnemonic PCLK 4 Processor Clock Test Clock TCK Test Mode Select TMS Test Data Input TDI Test Data Output TDO TRST 4 Test Reset Power Supply V CC Ground GND NOTES: 1. This signal is only available on the MC68040. ...

Page 106

... Freescale Semiconductor, Inc. ADDRESS A31–A0 BUS D31–D0 DATA BUS TT0 TT1 TM0 TM1 TM2 TLN0 TLN1 TRANSFER UPA0 ATTRIBUTES UPA1 R/W SIZ0 SIZ1 LOCK LOCKE CIOUT MASTER TS TRANSFER TIP CONTROL TA TEA SLAVE TCI TRANSFER TBI CONTROL DLE 1 NOTES: 1. This signal is only available on the MC68040. ...

Page 107

... Freescale Semiconductor, Inc. applications. Refer to Section 7 Bus Operation for detailed information about the relationship of the address bus to bus operation and the multiplexed bus mode. Refer to Appendix A MC68LC040 and Appendix B MC68EC040 for details concerning the CDIS level and multiplexed bus mode. 5.2 DATA BUS (D31–D0) These three-state bidirectional signals provide the general-purpose data path between the M68040 and all other devices ...

Page 108

... Freescale Semiconductor, Inc. 5.3.2 Transfer Modifier (TM2–TM0) These three-state outputs provide supplemental information for each transfer type. Table 5-3 lists the encoding for normal and MOVE16 transfers, and Table 5-4 lists the encoding for alternate access transfers. For interrupt acknowledge transfers, the TMx signals carry the interrupt level being acknowledged ...

Page 109

... Freescale Semiconductor, Inc. The TLNx signals can be used in high-performance systems to build an external snoop filter with a duplicate set of cache tags. The TLNx signals and address bus provide a direct indication of the state of the data caches and can be used to help maintain the duplicate tag store. The TLNx pins do not indicate the correct TLN number when an instruction cache burst fill occurs ...

Page 110

... Freescale Semiconductor, Inc. three-stating. Do not use LOCKE possible to retry the last write of a read-write- modify operation. 5.3.9 Cache Inhibit Out ( This three-state output reflects the state of the cache mode field in one of the address translation caches and is asserted for accesses to noncachable pages to indicate that an external cache should ignore the bus transfer ...

Page 111

... Freescale Semiconductor, Inc. the access. During alternate bus master accesses, the M68040 samples TEA to detect completion of each bus transfer. 5.4.5 Transfer Cache Inhibit ( This input signal inhibits read data from being loaded into the M68040 instruction or data caches. TCI is ignored during all writes and after the first data transfer for both burst line reads and burst-inhibited line reads ...

Page 112

... Freescale Semiconductor, Inc. cycle, the M68040 ignores all TA and TEA assertions while MI is asserted; when RSTI is asserted asserted. 5.6 ARBITRATION SIGNALS The following control signals support requests to an external arbiter to become the bus master. Refer to Section 7 Bus Operation for detailed information about the relationship of the arbitration signals to bus operation ...

Page 113

... Freescale Semiconductor, Inc. MC68040 Floating-Point Emulation (MC68040FPSP) for descriptions of emulator use of this signal. RSTI 5.7.2 Reset This input signal causes the M68040 to enter reset exception processing. The RSTI signal is an asynchronous input that is internally synchronized to the next rising edge of the BCLK signal. All three-state signals are set to the high-impedance state, and all outputs, except MI, are negated when RSTI is recognized ...

Page 114

... Freescale Semiconductor, Inc. 5.8.2 Interrupt Pending Status ( This output signal indicates that an interrupt request has been recognized internally and exceeds the current interrupt priority mask in the status register (SR). External devices (other bus masters) can use IPEND to predict processor operation on the next instruction boundaries ...

Page 115

... Freescale Semiconductor, Inc. Table 5-6. Processor Status Encoding Hex PST3 PST2 PST1 NOTE: *MC68040V and MC68EC040V only. When a ‘branch taken/end current instruction’ is indicated, it means that a change of instruction flow is pending. Along with the following instructions, an exception stacking (encoding F) sequence is ended with the ‘supervisor, branch taken/end current instruction’ ...

Page 116

... Freescale Semiconductor, Inc. The following examples are for PSTx encodings access error terminates an instruction such that the instruction execution stage is not reached. In this case, an ‘end current instruction’ is not indicated. Exception processing starts, the exception stacking status is indicated, and then the virtual JMP causes the ‘ ...

Page 117

... Freescale Semiconductor, Inc. 5.12 TEST SIGNALS The M68040 includes dedicated user-accessible test logic that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture . Problems associated with testing high-density circuit boards have led to the development of this standard under the IEEE Test Technology Committee and Joint Test Action Group (JTAG) sponsorship ...

Page 118

... Freescale Semiconductor, Inc. 5.14 SIGNAL SUMMARY Table 5-7 provides a summary of the electrical characteristics of the signals discussed in this section. Signal Name Address Bus Autovector Bus Busy Bus Clock Bus Grant Bus Request Cache Disable Cache Inhibit Out Data Bus Data Latch Enable 1 ...

Page 119

... Freescale Semiconductor, Inc. Table 5-7 Signal Summary (Continued) Signal Name Transfer Start Transfer Type Test Clock Test Data Input Test Data Output Test Mode Select Test Reset User-Programmable Attributes Power Supply NOTES: 1. This signal is not available on the MC68LC040 and MC68EC040. 2. These signals are different on power-up for the MC68LC040 and MC68EC040. ...

Page 120

... Freescale Semiconductor, Inc. SECTION 6 IEEE 1149.1A TEST ACCESS PORT (JTAG) This section does not apply to the MC68040V and MC68EC040V. Refer to Appendix C MC68040V and MC68EC040 for details. All references to M68040 in this section only, refer to the MC68040, MC68LC040, and MC68EC040. The M68040 includes dedicated user-accessible test logic that is fully compatible with the IEEE standard 1149.1A Standard Test Access Port and Boundary Scan Architecture . Problems associated with testing high-density circuit boards have led to the standard’ ...

Page 121

... Freescale Semiconductor, Inc. 6.1 OVERVIEW Figure 6-1 illustrates a block diagram of the M68040 implementation of IEEE standard 1149.1A. The test logic includes a 16-state dedicated TAP controller. These 16 controller states are defined in detail in the IEEE standard 1149.1A, but only 8 are included in this section. Test-Logic-Reset ...

Page 122

... Freescale Semiconductor, Inc. 6.2 INSTRUCTION SHIFT REGISTER The M68040 IEEE standard 1149.1A implementation includes a 3-bit instruction shift register without parity. The register shifts one of eight instructions, which can either select the test to be performed or access a test data register, or both. Data is transferred from the instruction shift register to latched decoded outputs during the update-IR state ...

Page 123

... Freescale Semiconductor, Inc. EXTEST asserts internal reset for the M68040 system logic to force a predictable benign internal state and activates an internal keep-alive clock to protect the device from potential internal damage. This internal clock eliminates the requirement to keep the system clocks (PCLK and BCLK) running during EXTEST operations and allows these two system clock pins to be included in boundary scan testing ...

Page 124

... Freescale Semiconductor, Inc. The DRVCTL.T instruction is intended to be used in test applications in conjunction with the EXTEST and SHUTDOWN instructions and not for system applications. It therefore differs from DRVCTL.S in that this instruction invokes the keep-alive clock, asserts the internal reset, and the test logic, not the system logic, has control of the I/O pins. ...

Page 125

... Freescale Semiconductor, Inc. has control of the I/O pins. The 1149.1A interface is transparent to system operation except for drive control selection during execution of this instruction. When the system logic has control of the signal I/O directions and levels, the drive control latches are loaded from the IPL2– IPL0 pins at the negation of the RSTI signal. After RSTI has been negated, and the 128-clock internal reset cycle has expired (see Section 7 Bus Operation), the DRVCTL ...

Page 126

... Freescale Semiconductor, Inc EXTEST, DRVCTL.T, AND SHUTDOWN 0 = OTHERWISE G1 DATA FROM 1 SYSTEM LOGIC MUX 1 Figure 6-3. Output Latch Cell (O.Latch) TO NEXT CELL TO SYSTEM LOGIC Figure 6-4. Input Pin Cell (I.Pin) MOTOROLA For More Information On This Product, TO NEXT CELL SHIFT MUX 1 C1 FROM ...

Page 127

... Freescale Semiconductor, Inc EXTEST 0 = OTHERWISE G1 OUTPUT CONTROL 1 FROM SYSTEM LOGIC MUX 1 Figure 6-5. Output Control Cells (IO.Ctl) OUTPUT ENABLE OUTPUT DATA INPUT DATA Figure 6-6. General Arrangement of Bidirectional Pins 6-8 For More Information On This Product, SHIFT DR TO NEXT CELL G1 1 MUX ...

Page 128

... Freescale Semiconductor, Inc. All M68040 bidirectional pins include two boundary scan data cells, an input, and an output. One of five associated boundary scan control cells controls each bidirectional pin. If these cells contain a logic one, the associated bidirectional or three-state pin will be configured as an output and enabled. The cell captures the current value during the capture-DR state ...

Page 129

... Freescale Semiconductor, Inc. Table 6-2. Boundary Scan Bit Definitions Pin/Cell Bit Cell Type Name Pin Type Output 2 0 O.Latch RSTO Output 2 1 O.Latch IPEND TS-Output 2 2 O.Latch CIOUT TS-Output 2 3 O.Latch UPA0 TS-Output 2 4 O.Latch UPA1 5 O.Latch TT0 6 I.Pin TT0 7 O.Latch ...

Page 130

... Freescale Semiconductor, Inc. Table 6-2. Boundary Scan Bit Definitions (Continued) Pin/Cell Bit Cell Type Name Pin Type 74 O.Latch D21 75 O.Latch D22 76 O.Latch D23 77 O.Latch D24 78 O.Latch D25 79 O.Latch D26 80 O.Latch D27 81 O.Latch D28 82 O.Latch D29 83 O.Latch D30 84 O.Latch D31 85 I.Pin ...

Page 131

... Freescale Semiconductor, Inc. Table 6-2. Boundary Scan Bit Definitions (Concluded) Pin/Cell Bit Cell Type Name Pin Type 148 I.Pin SIZ1 TS-Output 2 149 O.Latch LOCK 150 IO.Ctl io.ab 151 IO.Ctl io.db Output 2 152 O.Latch MI Output 2 153 O.Latch BR 154 IO.Ctl io.2 155 IO.Ctl io ...

Page 132

... Freescale Semiconductor, Inc. restarted, and a proper reentry into any of the four instructions is again required before the system clocks can be stopped. Control over the output enable signals using the boundary scan register and the EXTEST and HIGHZ instructions requires a compatible circuit-board test environment to avoid destructive configurations ...

Page 133

... Freescale Semiconductor, Inc. 6-14 For More Information On This Product, +5V 1K TDI TMS TRST TCLK NO CONNECTION TD0 Figure 6-7. Circuit Disabling IEEE Standard 1149.1A M68040 USER’S MANUAL Go to: www.freescale.com MOTOROLA ...

Page 134

... Freescale Semiconductor, Inc. 6.6 MOTOROLA M68040 BSDL DESCRIPTION (VERSION 2.2) Revision List: 1. LOCK and LOCKE controlled by io.1 vice io.0 (4D98D other changes to Version 2.1 BSDL. 2. Instruction opcodes changed for SAMPLE, SHUTDOWN, and BYPASS. 3. New instructions DRVCTL.T, DRVCTL.S and PRIVATE added. 4. New instructions DRVCTL.T and DRVCTL.S renamed to DRVCTL_T and DRVCTL_S for syntax compatibility ...

Page 135

... Freescale Semiconductor, Inc. DLE: in bit; PCLK: in bit; BCLK: in bit; IPL: in bit_vector(0 to 2); RSTI: in bit; CDIS: in bit; MDIS: in bit; EGND: linkage bit_vector(1 to 23); EVDD: linkage bit_vector(1 to 12); IGND: linkage bit_vector(1 to 12); IVDD: linkage bit_vector(1 to 7); CGND: linkage bit_vector(1 to 2); CVDD: linkage bit_vector(1 to 6); ...

Page 136

... Freescale Semiconductor, Inc. "TCI: T10, "DLE: T9, "PCLK: R9, "BCLK: R7, "IPL: (T8, T7, T6), "RSTI: S7, "CDIS: T5, "MDIS: S6, "EGND: (S2, Q2, N2, L2, H2, F2, D2, B2, B4, B6, B8, B10, " B13, B15, B17, D17, F17, H17, L17, N17, Q17, S17, S15), "EVDD: (R2, M2, G2, C2, B5, B9, B14, C17, G17, M17, R17, S16), " ...

Page 137

... Freescale Semiconductor, Inc. num cell port function "0 (BC_2, RSTO, output2, "1 (BC_2, IPEND, output2, "2 (BC_2, CIOUT, output3, "3 (BC_2, UPA(0), output3, "4 (BC_2, UPA(1), output3, "5 (BC_2, TT(0), output3, "6 (BC_4, TT(0), input, "7 (BC_2, TT(1), output3, "8 (BC_4, ...

Page 138

... Freescale Semiconductor, Inc. num cell port function "57 (BC_2, D(4), output3, "58 (BC_2, D(5), output3, "59 (BC_2, D(6), output3, "60 (BC_2, D(7), output3, "61 (BC_2, D(8), output3, "62 (BC_2, D(9), output3, "63 (BC_2, D(10), output3, "64 (BC_2, D(11), output3, "65 (BC_2, ...

Page 139

... Freescale Semiconductor, Inc. num cell port function "114 (BC_4, D(29), input, "115 (BC_4, D(30), input, "116 (BC_4, D(31), input, "117 (BC_2, A(9), output3, "118 (BC_4, A(9), input, "119 (BC_2, A(8), output3, "120 (BC_4, A(8), input, "121 (BC_2, A(7), output3, "122 (BC_4, ...

Page 140

... Freescale Semiconductor, Inc. num cell port function "171 (BC_4, SC(0), input, "172 (BC_4, TBI, input, "173 (BC_4, AVEC, input, "174 (BC_4, TCI, input, "175 (BC_4, DLE, input, "176 (BC_4, PCLK, input, "177 (BC_4, BCLK, input, "178 (BC_4, IPL(0), input, "179 (BC_4, ...

Page 141

... Freescale Semiconductor, Inc. JTAG Timing Specifications (All Operating Frequencies) Num Characteristic TCK Frequency of Operation 1 TCK Cycle Time 2 TCK Clock Pulse Width Measured at 1 TCK Rise and Fall Times 4 TRST Setup Time to TCK Falling Edge 5 TRST Assert Time 6 Boundary Scan Input Data Setup Time ...

Page 142

... Freescale Semiconductor, Inc. TCK DATA INPUTS DATA OUTPUTS DATA OUTPUTS DATA OUTPUTS Figure 6-10. Boundary Scan Timing Diagram TCLK TDI, TMS TDO TDO TDO Figure 6-11. Test Access Port Timing Diagram MOTOROLA For More Information On This Product INPUT DATA VALID 8 OUTPUT DATA VALID ...

Page 143

... Freescale Semiconductor, Inc. SECTION 7 BUS OPERATION The M68040 bus interface supports synchronous data transfers between the processor and other devices in the system. This section provides a functional description of the bus, the signals that control the bus, and the bus cycles provided for data transfer operations. ...

Page 144

... Freescale Semiconductor, Inc. negate logic levels. The exceptions to this rule are the TIP, TA, and B B signals that transition between logic levels during T4 but transition from a driven state to a high- impedance state during T1. The input setup time (t time (t ), and delay time ( timing specifications in Section 11 MC68040 Electrical and Thermal Characteristics ...

Page 145

... Freescale Semiconductor, Inc. 7.2 DATA TRANSFER MECHANISM Figure 7-2 illustrates how the bus designates operands for transfers on a byte boundary system. The integer unit handles floating-point operands as a sequence of related long- word operands. These designations are used in the figures and descriptions that follow. ...

Page 146

... Freescale Semiconductor, Inc REGISTER BYTE 3 MULTIPLEXER EXTERNAL D31–D24 DATA BUS ADDRESS BYTE 3 $xxxxxxx0 Table 7-1 lists the combinations of the SIZx, A1, and A0 signals, collectively called byte enable signals, that are used for each of the four sections of the data bus. In the table, BYTEn indicates the data bus section that is active, the portion of the requested operand that is read or written during that bus transfer ...

Page 147

... Freescale Semiconductor, Inc SIZ0 SIZ1 PAL16L8 U1 MC68040 Byte Data Select Generation. Motorola Worldwide Marketing Training Organization A0 A1 SIZ0 SIZ1 GND NC UUD UMD LMD LLD VCC /UUD = /A0 * /A1 + /SIZ1 * /SIZ0 + SIZ1 * SIZ0 /UMD = A0 * /A1 + /A1 * /SIZ1 + SIZ1 * SIZ0 + /SIZ1 * /SIZ0 /LMD = /A0 * /A1 + /SIZ1 * /SIZ0 ...

Page 148

... Freescale Semiconductor, Inc. Table 7-2. Summary of Access Types versus Bus Signal Encodings Data Cache Normal Bus Push Data/Code Signal Access Access A31–A0 Access Access Address Address UPA1, UPA0 $0 MMU Source 1 SIZ1, SIZ0 L/Line B/W/L/Line TT1, TT0 $0 $0 TM4–TM2 $0 $1,2, ...

Page 149

... Freescale Semiconductor, Inc. Figure 7-5 illustrates the transfer of a long-word operand from an odd address requiring more than one bus cycle. For the first transfer or bus cycle, the SIZx signals specify a byte transfer, and the byte offset is $1. The slave device supplies the byte and acknowledges the data transfer ...

Page 150

... Freescale Semiconductor, Inc. C1 BCLK A31– UPA1, UPA0 SIZ1 SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA D31–D24 D23–D16 D15–D8 D7–D0 Figure 7-7. Misaligned Long-Word Read Transfer Timing 7-8 For More Information On This Product BYTE WORD BYTE 0 BYTE 1 ...

Page 151

... Freescale Semiconductor, Inc. The combination of operand size and alignment determines the number of bus cycles required to perform a particular memory access. Table 7-3 lists the number of bus cycles required for different operand sizes with all possible alignment conditions for read and write cycles. The table confirms that alignment significantly affects bus cycle throughput for noncachable accesses ...

Page 152

... Freescale Semiconductor, Inc. 7.4.1 Byte, Word, and Long-Word Read Transfers During a read transfer, the processor receives data from a memory or peripheral device. Since the data read for a byte, word, or long-word access is not placed in either of the internal caches by definition, the processor ignores the level on the transfer cache inhibit (TCI) signal when latching the data ...

Page 153

... Freescale Semiconductor, Inc. C1 BCLK A31– UPA1, UPA0 SIZ1 SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA D31–D24 D23–D16 D15–D8 D7–D0 BYTE READ Figure 7-9. Byte, Word, and Long-WordRead Transfer Timing MOTOROLA For More Information On This Product BYTE ...

Page 154

... Freescale Semiconductor, Inc. Clock 1 (C1) The read cycle starts in C1. During the first half of C1, the processor places valid values on the address bus and transfer attributes. For user and supervisor mode accesses, which the corresponding memory unit translates, the user-programmable attribute signals (UPAx) are driven with the values from the matching user bits (U1 and U0) ...

Page 155

... Freescale Semiconductor, Inc. the data bus and asserting TA. A line transfer performed in this manner with a single address is referred line burst transfer. The M68040 also supports burst-inhibited line transfers for memory devices that are unable to support bursting. For this type of bus cycle, the selected device supplies the first long word pointed to by the processor address and asserts transfer burst inhibit (TBI) with TA for the first transfer of the line access ...

Page 156

... Freescale Semiconductor, Inc. PROCESSOR ADDRESS DEVICE 1) SET R/W TO READ 2) DRIVE ADDRESS ON A31–A0 3) DRIVE USER PAGE ATTRIBUTES ON UPA1, UPA0 4) DRIVE SIZE ON SIZ1, SIZ0 (LINE) 5) DRIVE TRANSFER TYPE ON TT1, TT0 6) DRIVE TRANSFER MODIFIER ON TM2–TM0 7) CIOUT BECOMES VALID 8) ASSERT TS FOR ONE CLOCK ...

Page 157

... Freescale Semiconductor, Inc. BCLK A31–A4 A3 A2–A0 UPA1, UPA0 SIZ1, SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA TCI D31–D0 NOTE: The selected device increments the value of A3 and A2. Figure 7-11. Line Read Transfer Timing Clock 1 (C1) The line read cycle starts in C1. During the first half of C1, the processor places valid values on the address bus and transfer attributes ...

Page 158

... Freescale Semiconductor, Inc. (Except MC68EC040 and MC68EC040V) for information on the M68040 and MC68LC040 memory units and Appendix B MC68EC040 for information on the MC68EC040 memory unit. The processor asserts TS during C1 to indicate the beginning of a bus cycle. If not already asserted from a previous bus cycle, TIP is also asserted at this time to indicate that a bus cycle is active ...

Page 159

... Freescale Semiconductor, Inc. Clock 5 (C5) This clock is identical to C3 except that once TA is recognized, the latched value corresponds to the third long word of data for the burst. After the processor recognizes the last TA assertion and terminates the line read bus cycle, TIP remains asserted if the processor is ready to begin another bus cycle ...

Page 160

... Freescale Semiconductor, Inc. PROCESSOR ADDRESS DEVICE 1) SET R/W TO READ 2) DRIVE ADDRESS ON A31–A0 3) DRIVE USER PAGE ATTRIBUTES ON UPA1, UPA0 4) DRIVE SIZE ON SIZ1, SIZ0 (LINE) 5) DRIVE TRANSFER TYPE ON TT1, TT0 6) DRIVE TRANSFER MODIFIER ON TM2–TM0 7) CIOUT BECOMES VALID 8) ASSERT TS FOR ONE CLOCK ...

Page 161

... Freescale Semiconductor, Inc. C1 BCLK A31– A1, A0 UPA1, UPA0 SIZ1, SIZ0 LINE TT1, TT0 TM2–TM0 TLN1, TLN0 R/W CIOUT TS TIP TA TBI TCI D31–D0 INHIBITED LINE READ Figure 7-13. Burst-Inhibited Line Read Transfer Timing MOTOROLA For More Information On This Product, ...

Page 162

... Freescale Semiconductor, Inc. 7.4.3 Byte, Word, and Long-Word Write Transfers During a write transfer, the processor transfers data to a memory or peripheral device. The level on the TCI signal is ignored by the processor during all write cycles. The bus controller performs byte, word, and long-word write transfers for the following cases: • ...

Page 163

... Freescale Semiconductor, Inc. Figure 7-15. Long-Word Write Transfer Timing Clock 1 (C1) The write cycle starts in C1. During the first half of C1, the processor places valid values on the address bus and transfer attributes. For user and supervisor mode accesses, which the corresponding memory unit translates, the UPAx signals are driven with the values from the U1 and U0 bits for the area ...

Page 164

... Freescale Semiconductor, Inc. Clock 2 (C2) During the first half of the clock after C1, the processor negates TS and drives the appropriate bytes of the data bus with the data to be written. All other bytes are driven with undefined values. The selected device uses R/W, SIZ1, SIZ0, A1, A0, and CIOUT to latch only the required information on the data bus. With the exception of R/W and CIOUT, these signals also select any or all of the bytes (D31– ...

Page 165

... Freescale Semiconductor, Inc. PROCESSOR ADDRESS DEVICE 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON A31–A0 3) DRIVE USER PAGE ATTRIBUTES ON UPA1, UPA0 4) DRIVE SIZE ON SIZ1, SIZ0 (LINE) 5) DRIVE TRANSFER TYPE ON TT1, TT0 6) DRIVE TRANSFER MODIFIER ON TM2–TM0 7) CIOUT BECOMES VALID 8) ASSERT TS FOR ONE CLOCK ...

Page 166

... Freescale Semiconductor, Inc. BCLK A31–A4 A3 A2–A0 UPA1, UPA0 SIZ1, SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA D31–D0 NOTE: The selected device increments the value of A3 and A2. Figure 7-17. Line Write Transfer Timing Clock 1 (C1) The line write cycle starts in C1. During the first half of C1, the processor places valid values on the address bus and transfer attributes ...

Page 167

... Freescale Semiconductor, Inc. MC68LC040 memory units and Appendix B MC68EC040 for information on the MC68EC040 memory unit. The processor asserts TS during C1 to indicate the beginning of a bus cycle. If not already asserted from a previous bus cycle, the TIP signal is also asserted at this time to indicate that a bus cycle is active. ...

Page 168

... Freescale Semiconductor, Inc. 7.4.5 Read-Modify-Write Transfers (Locked Transfers) The read-modify-write transfer performs a read, conditionally modifies the data in the processor, and writes the data out to memory. In the M68040, this operation can be indivisible, providing semaphore capabilities for multiprocessor systems. During the entire read-modify-write sequence, the M68040 asserts the LOCK signal to indicate that an indivisible operation is occurring and asserts the LOCKE signal for the last transfer to indicate completion of the locked sequence ...

Page 169

... Freescale Semiconductor, Inc. BCLK A31–A0 UPA1, UPA0 SIZ1 SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT LOCK LOCKE TS TIP TA D31–D24 D23–D16 D15–D8 D7–D0 Undefined Figure 7-18. Locked Transfer for TAS Instruction Timing MOTOROLA For More Information On This Product, ...

Page 170

... Freescale Semiconductor, Inc. Clock 2 (C2) During the first half of the first clock cycle after C1, the processor negates TS. The selected device uses R/W, SIZ1, SIZ0, A1, and A0 to place its information on the data bus. With the exception of R/W, these signals also select any or all of the bytes (D24– ...

Page 171

... Freescale Semiconductor, Inc. When the processor recognizes TA at the end of a clock, the bus cycle is terminated, but TIP remains asserted if the processor is ready to begin another bus cycle. Otherwise, the processor negates TIP during the first half of the next clock. The processor also three-states the data bus during the first half of the next clock following termination of the write cycle ...

Page 172

... Freescale Semiconductor, Inc. OTHERWISE Figure 7-19. Interrupt Pending Procedure The M68040 asserts IPEND when an interrupt request is pending. Figure 7-20 illustrates the assertion of IPEND relative to the assertion of an interrupt level on the IPL≈ signals. IPEND signals external devices that an interrupt exception will be taken at an upcoming instruction boundary (following any higher priority exception) ...

Page 173

... Freescale Semiconductor, Inc. The M68040 takes an interrupt exception for a pending interrupt within one instruction boundary after processing any other pending exception with a higher priority. Thus, the M68040 executes at least one instruction in an interrupt exception handler before recognizing another interrupt request. The following paragraphs describe the various kinds of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing ...

Page 174

... Freescale Semiconductor, Inc. The interrupt acknowledge bus cycle is a read transfer. It differs from a normal read cycle in the following respects: 1. TT1 and TT0 = $3 to indicate an acknowledged bus cycle. 2. Address signals A31–A0 are set to all ones ($FFFFFFFF). 3. TM2–TM0 are set to the interrupt request level (the inverted values of IPL2–IPL0). ...

Page 175

... Freescale Semiconductor, Inc. BCLK A31–A0 UPA1, UPA0 SIZ1 SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA AVEC D31–D8 D7–D0 Figure 7-22. Interrupt Acknowledge Bus Cycle Timing 7.5.1.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE BUS CYCLE. When the interrupting device cannot supply a vector number, it requests an automatically generated vector (autovector) ...

Page 176

... Freescale Semiconductor, Inc. generates the vector number, which is the sum of the interrupt priority level plus 24 ($18). There are seven distinct autovectors that can be used, corresponding to the seven levels of interrupts available with IPL2–IPL0 signals. Figure 7-23 illustrates a functional timing diagram for an autovector operation. ...

Page 177

... Freescale Semiconductor, Inc. 7.5.2 Breakpoint Interrupt Acknowledge Bus Cycle The execution of a breakpoint instruction (BKPT) generates the breakpoint interrupt acknowledge bus cycle. An acknowledged access is indicated with TT1 and TT0 = $3, address A31–A0 = $00000000, and TM2–TM0 = $0. When the external device terminates the cycle with either TA or TEA, the processor takes an illegal instruction exception ...

Page 178

... Freescale Semiconductor, Inc. BCLK A31–A0 UPA1, UPA0 SIZ1 SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA D31–D0 Figure 7-25. Breakpoint Interrupt Acknowledge Bus Cycle Timing 7.6 BUS EXCEPTION CONTROL CYCLES The M68040 bus architecture requires assertion of TA from an external device to signal that a bus cycle is complete not asserted in the following cases: • ...

Page 179

... Freescale Semiconductor, Inc. To properly control termination of a bus cycle for a bus error or retry condition, TA and TEA must be asserted and negated for the same rising edge of BCLK. Table 7-5 lists the control signal combinations and the resulting bus cycle terminations. Bus error and retry terminations during burst cycles operate as described in 7 ...

Page 180

... Freescale Semiconductor, Inc. buffer into the cache to eliminate an unnecessary push access bus error occurs during a data cache push, the corresponding cache line remains valid (with the new line data) if the line push follows a replacement line read invalidated if a CPUSH instruction explicitly forces the push. Write accesses to memory pages specified as write- through by the data memory unit update the corresponding cache line before accessing memory ...

Page 181

... Freescale Semiconductor, Inc. BCLK A31–A0 UPA1, UPA0 SIZ1 SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA TEA D31–D0 Figure 7-26. Word Write Access Terminated with MOTOROLA For More Information On This Product WORD WRITE CYCLE WRITE STACK M68040 USER’S MANUAL Go to: www ...

Page 182

... Freescale Semiconductor, Inc. BCLK A31–A4 A3 A2–A0 UPA1, UPA0 SIZ1, SIZ0 TT1, TT0 TM2–TM0 R/W CIOUT TS TIP TA TEA TBI D31–D0 NOTE: The selected device increments the value on A3 and A2. Figure 7-27. Line Read Access Terminated with 7-40 For More Information On This Product, ...

Page 183

... Freescale Semiconductor, Inc. 7.6.2 Retry Operation When an external device asserts both the TA and TEA signals during a bus cycle, the processor enters the retry sequence. The processor terminates the bus cycle and immediately retries the cycle using the same access information (address and transfer attributes) ...

Page 184

... Freescale Semiconductor, Inc. On the initial cycle of a line transfer, a retry causes the processor to retry the bus cycle as illustrated in Figure 7-29. However, the processor recognizes a retry signaled during the second, third, or fourth cycle of a line as a bus error and causes the processor to abort the line transfer ...

Page 185

... Freescale Semiconductor, Inc. 7.6.3 Double Bus Fault A double bus fault occurs when an access or address error occurs during the exception processing sequence—e.g., the processor attempts to stack several words containing information about the state of the machine while processing an access error exception bus error occurs during the stacking operation, the second error is considered a double bus fault. The M68040 indicates a double bus fault condition by continuously driving PST3– ...

Page 186

... Freescale Semiconductor, Inc. on the operand read itself can cause the instruction to be aborted, preventing multiple reads important to note that when memory accesses are serialized noncachable, FMOVE will cause two identical writes to the same location to occur if the next instruction prefetch receives a bus error. ...

Page 187

... Freescale Semiconductor, Inc. be continuously granted to the processor, and no arbiter is needed. Systems that include several devices that can become bus masters require an arbiter to assign priorities to these devices so that, when two or more devices simultaneously attempt to become the bus master, the one having the highest priority becomes the bus master first. ...

Page 188

... Freescale Semiconductor, Inc. In the second situation, the processor samples BB until the external bus arbiter negates BB. The processor drives its output pins with undetermined values and three-states BB, but does not perform a bus cycle. This procedure, called implicit ownership of the bus, occurs when the processor is granted the bus but there are no pending bus cycles internal access request is generated, the processor assumes explicit ownership of the bus and immediately begins an access, simultaneously asserting BB, BR, TIP, and TS ...

Page 189

... Freescale Semiconductor, Inc. BBI *BG IBR BG IMPLICIT OWNERSHIP, *BG IBR BBO DRIVEN BY MC68040, THREE-STATED *ENDCYCLE BBI *BG BB BBI BBO BR IBR D Q BCLK Figure 7-30. M68040 Internal Interpretation State Diagram and MOTOROLA For More Information On This Product, *BG TSI *BBI BG TSI *BG IDLE, BBO DRIVEN BY MC68040, ...

Page 190

... Freescale Semiconductor, Inc. Table 7-6. M68040 Bus Arbitration States BB BG Negated Negated Negated Asserted Asserted Negated Asserted Asserted Alternate Bus Master Ownership Asserted Asserted The M68040 can be in the active bus cycle, park, or implicit ownership states when BG is negated. Depending on the state the processor is in when BG is negated, uncertain conditions can occur ...

Page 191

... Freescale Semiconductor, Inc. 040_BG 040_BB 040_TS 040_TA 040_LOCK * AM_BG * AM_BB * AM_TS POSSIBLE INDETERMINATE CONDITION * AM indicates the alternate bus master. Figure 7-31. Lock Violation Example In addition to the indeterminate condition, the external arbiter’s design needs to include the function of BR. For example, in certain cases associated with conditional branches, ...

Page 192

... Freescale Semiconductor, Inc. require a pullup resistor to maintain a logic-one level between bus master tenures. The alternate bus master should negate these signals before three-stating to minimize rise time of the signals and ensure that the processor recognizes the correct level on the next BCLK rising edge. At the end of C3, the processor recognizes the bus grant and bus idle conditions (BG asserted and BB negated) and assumes ownership of the bus by asserting BB and immediately beginning a bus cycle during C4 ...

Page 193

... Freescale Semiconductor, Inc. Figure 7-33 illustrates a functional timing diagram for an arbitration of a relinquish and retry operation. Figure 7- functional timing diagram for implicit ownership of the bus. In Figure 7-33, the processor read access that begins terminated at the end of C2 with a retry request and BG negated, forcing the processor to relinquish the bus and allow the alternate master to access the bus ...

Page 194

... Freescale Semiconductor, Inc. C1 BCLK A31–A0 TRANSFER ATTRIBUTES TS TIP TA D31– AM_BR * AM_BG ALTERNATE MASTER * AM indicates the alternate bus master. Undefined Figure 7-34. Implicit Bus Ownership Arbitration Timing 7.8.2 Bus Arbitration Examples The following paragraphs illustrate the behavior of the M68040 bus arbitration scheme and provide examples of how an external bus arbiter can be designed to keep the integrity of locked bus operations ...

Page 195

... Freescale Semiconductor, Inc. how the LOCKE signal can be used to end a locked sequence and to yield the bus one bus cycle earlier than is normally possible. Figure 7-35 illustrates the state diagram of a hypothetical external arbiter design. BB LOCK LOCK LOCKE STATE D BG1*, BG2 BB* ...

Page 196

... Freescale Semiconductor, Inc. give the bus to processor 2. The arbiter remains in state B until BB is negated, signifying the end of the bus cycle. Once state C is reached, depending on whether or not processor 2 asserts BR2 and then negates BR2 because of a disregard request condition, processor 1 may or may not actively begin a bus cycle ...

Page 197

... Freescale Semiconductor, Inc. BB BR2* STATE D BG1*, BG2 BB* BR2* V BR2 LOCK LOCKE* BG1*, BG2 STATE A NOTES: 1. Because this example uses two MC68040s refers to the processor and its signals. 2. *Indicates the signal is asserted for that device. Figure 7-36. Dual M68040 Prioritized Arbitration State Diagram 7 ...

Page 198

... Freescale Semiconductor, Inc. BB STATE D AM_BG, 040_BG* BB* 040_BR V AM_BR* AM_BG, 040_BG* STATE A (a) MC68040 High Priorty, Default Bus Master BB AM_BR* STATE D AM_BG, 040_BG* BB* AM_BR* V AM_BR LOCK LOCKE* AM_BG, 040_BG* STATE A * Indicates the signal is asserted for that device. (b) MC68040 Low-Priorty, Default Bus Master Figure 7-37 ...

Page 199

... Freescale Semiconductor, Inc. 7.8.2.4 M68040 ASYNCHRONOUS DMA ARBITRATION. Figure 7-38 illustrates a sample synchronizer circuit. Figure 7-39 illustrates how an M68040 can be implemented to simulate an MC68030. The synchronizer circuit has an output indicating whether or not a signal has been asserted for at least two consecutive rising edges of BCLK. If the synchronizer circuit indicates that the input has not been stable for at least two clocks, then the processor and alternate bus master stay in the current state ...

Page 200

... Freescale Semiconductor, Inc LOCK LOCKE AM_BG*, LOCK* 040_BG LOCK LOCKE RV LOCK LOCKE* (a) MC68040 Low-Priorty, Default Bus Master R RV 040_BR AM_BG*, 040_BG 040_BR R* V RV* V 040_BR NOTES assumed that the asynchronous device takes the bus only after TIP or the MC68040 negated. 2. *Indicates the signal is asserted for that device. ...

Related keywords