MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 109

IC MICROPROCESSOR 32BIT 184-CQFP

MC68040FE33A

Manufacturer Part Number
MC68040FE33A
Description
IC MICROPROCESSOR 32BIT 184-CQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68040FE33A

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Package
184CQFP
Processor Series
M680xx
Core
CPU32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68040FE33A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor, Inc.
The TLNx signals can be used in high-performance systems to build an external snoop
filter with a duplicate set of cache tags. The TLNx signals and address bus provide a
direct indication of the state of the data caches and can be used to help maintain the
duplicate tag store. The TLNx pins do not indicate the correct TLN number when an
instruction cache burst fill occurs.
5.3.4 User-Programmable Attributes (UPA1, UPA0)
The UPAx signals are three-state outputs. If they match the logical address, the user-
programmable attribute bits in the address translation entry or the transparent translation
register determine the UPAx signal level. These signals are only for normal code, data,
and MOVE16 accesses. For all other accesses, including table search and cache line
push accesses, which may result from a normal access, the UPAx signals are zero. If the
transparent translation register and the memory management unit are disabled, the UPAx
signals are also zero. When the M68040 is not the bus master, these signals are set to a
high-impedance state.
W
5.3.5 Read/Write (R/
)
This bidirectional three-state signal defines the data transfer direction for the current bus
cycle. A high level indicates a read cycle, and a low level indicates a write cycle. The bus
snoop controller examines this signal when the processor is not the bus master.
5.3.6 Transfer Size (SIZ1, SIZ0)
These bidirectional three-state signals indicate the data size for the bus transfer. The bus
snoop controller examines this signal when the processor is not the bus master. Refer to
Section 7 Bus Operation for more information on the encoding of these signals.
LOCK
5.3.7 Lock (
)
This three-state output indicates that the current transfer is part of a sequence of locked
transfers for a read-modify-write operation. The external arbiter can use LOCK to prevent
an alternate bus master from gaining control of the bus and accessing the same operand
between processor accesses for the locked sequence of transfers. Although LO CK
indicates that the processor requests the bus be locked, the processor will give up the bus
if the external arbiter negates the BG signal. When the M68040 is not the bus master, the
LOCK signal is set to a high-impedance state. LOCK drives high before three-stating.
Refer to Section 7 Bus Operation for information on locked transfers.
LOCKE
5.3.8 Lock End (
)
This three-state output indicates that the current transfer is the last in a sequence of
locked transfers for a read-modify-write operation. The external arbiter can use LOCKE to
support arbitration between unrelated locked transfer sequences while still maintaining the
indivisible nature of each read-modify-write operation. When the M68040 is not the bus
master, the LOCKE signal is set to a high-impedance state. LOCKE drives high before
MOTOROLA
M68040 USER’S MANUAL
5- 7
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