MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 131

IC MICROPROCESSOR 32BIT 184-CQFP

MC68040FE33A

Manufacturer Part Number
MC68040FE33A
Description
IC MICROPROCESSOR 32BIT 184-CQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68040FE33A

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Package
184CQFP
Processor Series
M680xx
Core
CPU32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68040FE33A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
NOTES:
6.4 RESTRICTIONS
The test logic is implemented using static logic design, and TCK can be stopped in either
a high or low state without loss of data. The system logic, however, includes considerable
dynamic logic. For this reason, the system clocks (PCLK and BCLK) cannot be stopped or
allowed to run slower than the specified frequency except when the EXTEST, HIGHZ,
DRVCTL.T, or SHUTDOWN instructions have been properly invoked.
PCLK and BCLK must be kept running for two additional BCLK periods upon initial entry
into any of the four instructions, EXTEST, HIGHZ, DRVCTL.T, or SHUTDOWN. This
restriction is necessary to allow time for an internal reset to propagate through an internal
synchronizer. After this period, the user has complete time-domain freedom with the two
system clock pins. After any of the four instructions has been properly entered, these
instructions can be executed in any order without a time-domain clocking restriction.
Entering any instruction other than one of these four requires that the system clocks be
6-12
1. I.Pin, IO.Ctl, and O.Latch are equivalent to the BSDL descriptions: BC_4, BC_2, and BC_2, respectively.
2. Boundary scan register bit positions that are used during the drive control (DRVCTL.X) instructions.
3. These output-only cells can be turned off (high impedance) by using the HIGHZ instruction.
4. All of the control signals (IO.Ctl) are cleared in the test-logic-reset state.
5. Renamed JS0 on the MC68LC040 and MC68EC040.
6. Renamed JS1 on the MC68EC040.
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
Bit
Cell Type
O.Latch
O.Latch
O.Latch
O.Latch
O.Latch
O.Latch
O.Latch
O.Latch
O.Latch
O.Latch
IO.Ctl
IO.Ctl
IO.Ctl
IO.Ctl
IO.Ctl
I.Pin
I.Pin
I.Pin
Table 6-2. Boundary Scan Bit Definitions (Concluded)
Pin/Cell
Name
LOCK
PST3
PST2
PST1
PST0
SIZ1
io.ab
io.db
io.2
io.1
io.0
TIP
BR
TS
TS
BB
BB
MI
Freescale Semiconductor, Inc.
For More Information On This Product,
TS-Output 2
TS-Output 2
Pin Type
Output 2
Output 2
Output 2
Output 2
Output 2
Output 2
I/O 2
I/O 2
I/O
I/O
I/O
M68040 USER’S MANUAL
Go to: www.freescale.com
Ctrl Cell
(Note 4)
(Note 4)
(Note 3)
(Note 3)
(Note 4)
(Note 4)
(Note 4)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
Output
io.0
io.1
io.0
io.0
io.1
io.1
io.1
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
Bit
Cell Type
O.Latch
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
I.Pin
Pin/Cell
MDIS 6
Name
AVEC
DLE 5
PCLK
BCLK
CDIS
RSTI
TEA
SC1
SC0
IPL0
IPL1
IPL2
TBI
TCI
TA
TA
BG
Pin Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O 2
I/O
MOTOROLA
Ctrl Cell
Output
io.2
io.2

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