MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 185

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
7.6.3 Double Bus Fault
A double bus fault occurs when an access or address error occurs during the exception
processing sequence—e.g., the processor attempts to stack several words containing
information about the state of the machine while processing an access error exception. If
a bus error occurs during the stacking operation, the second error is considered a double
bus fault.
The M68040 indicates a double bus fault condition by continuously driving PST3–PST0
with an encoded value of $5 until the processor is reset. Only an external reset operation
can restart a halted processor. While the processor is halted, negating BR and forcing all
outputs to a high-impedance state releases the external bus.
A second access or address error that occurs during execution of an exception handler or
later, does not cause a double bus fault. A bus cycle that is retried does not constitute a
bus error or contribute to a double bus fault. The processor continues to retry the same
bus cycle as long as external hardware requests it.
7.7 BUS SYNCHRONIZATION
The M68040 integer unit generates access requests to the instruction and data memory
units to support integer and floating-point operations. Both the <ea> fetch and write-back
stages of the integer unit pipeline perform accesses to the data memory unit, with effective
address fetches assigned a higher priority. This priority allows data read and write
accesses to occur out of order, with a memory write access potentially delayed for many
clocks while allowing read accesses generated by later instructions to complete. The
processor detects a read access that references earlier data waiting to be written (address
collisions) and allows the corresponding write access to complete. A given sequence of
read accesses or write accesses is completed in order, and reordering only occurs with
writes relative to reads. Figure 2-1 in Section 2 Integer Unit illustrates the integer pipeline
stages.
Besides address collisions, the instruction restart model used for exception processing in
the M68040 causes another potential problem. After the operand fetch for an instruction,
an exception that causes the instruction to be aborted can occur, resulting in another
access for the operand after the instruction restarts. For example, an exception could
occur after a read access of an I/O device’s status register. The exception causes the
instruction to be aborted and the register to be read again. If the first read accesses clears
the status bits, the status information is lost, and the instruction obtains incorrect data.
Designating the memory page containing the address of the device as serialized
noncachable prevents multiple out-of-order accesses to devices sensitive to such
accesses. When the data memory unit detects an attempt to read an operand from a page
designated as serialized noncachable, it allows all pending write accesses to complete
before beginning the external read access. The definition of a page as noncachable
versus serialized noncachable only affects read accesses. When a write operation
reaches the integer unit’s write-back stage, all previous instructions have completed.
When a read access to a serialized noncachable page begins, only a bus error exception
MOTOROLA
M68040 USER’S MANUAL
7- 43
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