MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 201

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
7.9 BUS SNOOPING OPERATION
When required, the M68040 can monitor alternate bus master transfers and intervene in
the access to maintain cache coherency. The encoding of the SCx signals generated by
the alternate bus master for each bus cycle controls the process of bus monitoring and
intervention called snooping. Only byte, word, long-word, and line bus transfers can be
snooped. Refer to Section 4 Instruction and Data Caches for SCx encodings.
When the M68040 recognizes that an alternate bus master has asserted T S, the
processor latches the level on the byte offset, SIZx, TMx, and R/W signals during the
rising edge of BCLK for which TS is first asserted. The processor then evaluates the SCx
and TTx signals to determine the type of access (TTx = $0 or $1), if it is snoopable, and, if
so, how it should be snooped. If snooping is enabled for the access, the processor inhibits
memory from responding by continuing to assert the memory inhibit signal (MI) while
checking the internal caches for matching lines. During the snooped bus cycle, the
M68040 ignores all TA assertions while MI is asserted. Unless the data cache contains a
dirty line corresponding to the access and the requested snoop operation indicates sink
data for a write or source data for a read, M I is negated, and memory is allowed to
respond and complete the access. Otherwise, the processor continues to intervene in the
access by keeping MI asserted and responding to the alternate bus master as a slave
device. The processor monitors the levels of TA, TEA, and TBI to detect normal, bus error,
retry, and burst-inhibited terminations. Note that for alternate bus master burst-inhibited
line transfers, the M68040 snoops each of the four resulting long-word transfers. If
snooping is disabled, MI is negated, and the M68040 counts the appropriate number of TA
or TEA assertions before proceeding. For example, if the SIZx signals are pulled high, the
M68040 requires four TA assertions, one TEA assertion, or one retry termination before
proceeding.
As a bus master, the M68040 can be configured to request snooping operations on a
page-by-page basis. The UPAx signals are connected to the SCx inputs of the snooping
processors. Appropriately programming the user attribute bits in the corresponding page
descriptor selects the required snooping operation for a page. Refer to Section 3 Memory
Management Unit (Except MC68EC040 and MC68EC040V) for details on configuring
the caching mode and user attribute bits for each memory page for the M68040 and
MC68LC040, and refer to Appendix B MC68EC040 for the MC68EC040.
In a system with multiple bus masters, the memory unit must wait for each snooping bus
master to negate MI before responding to an access. A termination signal asserted before
the negation of MI leads to undefined operation and must be avoided at all costs. Also, if
the system contains multiple caching masters, then each master must access shared data
using write-through pages that allow writes to the data to be snooped by other masters.
The copyback caching mode is typically used for data local to a processor because in a
multimaster caching system only one master at a time can access a given page of
copyback data. The copyback caching mode also prevents multiple snooping processors
from intervening in a specific access.
MOTOROLA
M68040 USER’S MANUAL
7- 59
For More Information On This Product,
Go to: www.freescale.com