MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 219

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

8.2.1 Access Fault Exception
An access fault exception occurs when a data or instruction prefetch access faults due to
either an external bus error or an internal access fault. Both types of access faults are
treated identically and the access fault exception handler or a status bit in the access fault
stack frame distinguishes them. An access fault exception may or may not be taken
immediately, depending on whether the faulted access specifically references data
required by the execution unit or whether there are any other exceptions that can occur,
allowing the execution pipeline to idle.
An external access fault (bus error) occurs when external logic aborts a bus cycle and
asserts the TEA input signal. A bus error on a data write access always results in an
access fault exception, causing the processor to begin exception processing immediately.
A bus error on a data read also causes exception processing to begin immediately if the
access is a byte, word, or long-word access or if the bus error occurs on the first transfer
of a line read. Bus errors on the second, third, or fourth transfers for a data line read
cause the transfer to be aborted, but result in a bus error only if the execution unit is
specifically requesting the long word being transferred. For example, if a misaligned
operand spans the first two long words in the line being read, a bus error on the second
transfer causes an exception, but a bus error on the third or last transfer does not, unless
the execution unit has generated another operand access that references data in these
transfers.
Bus errors that occur during instruction prefetches are deferred until the processor
attempts to use the information. For instance, if a bus error occurs while prefetching other
instructions after a change-of-flow instruction (BRA, JMP, JSR, TRAP#n, etc.), BRA, JMP,
JSR, TRAP#n execution of the new instruction flow clears the exception condition. This
also applies to the not-taken branch for a conditional branch instruction, even though both
sides of the branch are decoded.
Processor accesses for either data or instructions can result in internal access faults.
Internal access faults must be corrected to complete execution of the current context. Four
types of internal access faults can occur:
8-6
• Trace
• Format Error
• Breakpoint Instruction
• Interrupt
• Reset
1. Push transfer faults occur when the execution unit is idle, the integer unit pipeline is
2. Data access faults occur when the bus controller and the execution unit are idle. A
frozen, the instruction and data cache requests are cancelled (however, writes are
not lost), and pending writes are stacked.
data access fault freezes the pipeline and cancels any pending instruction cache
accesses. Pending writes are stacked because the data cache is deadlocked until
stacking transfers are initiated.
Freescale Semiconductor, Inc.
For More Information On This Product,
M68040 USER’S MANUAL
Go to: www.freescale.com
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