MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 278

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

final result). If the exception is enabled, the underflow should be signaled any time a very
small result is produced, regardless of whether accuracy is lost in calculating it.
The processor UNFL bit in the FPSR AEXC byte implements the IEEE exception disabled
definition since it is only set when a very small number is generated and accuracy has
been lost when calculating that number. The UNFL bit in the FPCR EXC byte implements
the IEEE exception enabled definition since it is set any time a tiny number is generated.
9.7.5.1 MASKABLE EXCEPTION CONDITIONS. There are no conditions.
9.7.5.2 NONMASKABLE EXCEPTION CONDITIONS. When the UNFL bit of the FPSR is
set, the processor always takes an exception regardless of whether or not the user UNFL
exception handler is enabled. If the destination is a floating-point data register, the register
is not affected, and either a pre-instruction or a post-instruction exception is reported. If
the destination is a memory or integer data register, then an undefined result is stored,
and a post-instruction exception is taken immediately. Exception processing begins with
the M68040FPSP UNFL exception handler.
The M68040FPSP UNFL exception handler stores the result in the destination as either a
denormalized number or zero. Shifting the mantissa of the intermediate result to the right
while incrementing the exponent until it is equal to the denormalized exponent value for
the destination format accomplishes denormalization. The denormalized intermediate
result is rounded to the selected rounding precision if the destination is a floating-point
data register or rounded to the destination format in the case of an FMOVE OUT
instruction. For the instructions with forced rounding precision (e.g., FSADD and FDMUL),
the destination is rounded using the precision defined by the instruction.
If in the process of denormalizing the intermediate result, all of the most significant bits are
shifted off to the right, the selected rounding mode determines the value to be stored at
the destination, Table 9-13 lists these values. Once the result is stored in the destination,
the M68040FPSP UNFL exception handler checks to see if the user UNFL exception
handler is enabled.
9-34
Rounding
Mode
RN
RM
RP
RZ
Table 9-13. Underflow Rounding Mode Values
Zero, with the sign of the intermediate result.
Zero, with the sign of the intermediate result.
For positive overflow, + zero; for negative underflow, smallest denormalized
negative number.
For positive overflow, smallest denormalized positive number; for negative
underflow, –zero.
Freescale Semiconductor, Inc.
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