MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 296

IC MICROPROCESSOR 32BIT 184-CQFP

MC68040FE33A

Manufacturer Part Number
MC68040FE33A
Description
IC MICROPROCESSOR 32BIT 184-CQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68040FE33A

Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Package
184CQFP
Processor Series
M680xx
Core
CPU32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68040FE33A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
10.2 INSTRUCTION TIMING EXAMPLES
The following examples utilize the instruction timing information given in this section.
Figure 10-1 illustrates the integer unit pipeline flow for the simple code sequence listed.
The three instructions in the code sequence require only a single clock in each pipeline
stage. The TRAPF instructions are also single-clock instructions that function as
nonsynchronizing NOPs.
MOTOROLA
C1 The previous instruction (P1) finishes in the <ea> calculate.
C2 MOVE.L (A) starts in the <ea> calculate and requests an immediate extension
C3 MOVE.L (A) starts in the <ea> fetch, which fetches the operand at $1000. ADDQ.L
C4 MOVE.L (A) executes in the execute stage, storing the fetched operand in register
C5 ADDQ.L (B) executes in the execution stage, incrementing D0 by 1. MOVE.L (C)
C6 MOVE.L (C) executes in the execution stage generating a write of D0 to the
C7 The write to memory by MOVE.L (C) occurs to the data memory unit if it is not
word for its effective address.
(B) starts in the <ea> calculate stage with the operand encoded in the instruction.
D0. ADDQ.L (B) starts in the <ea> fetch with no operation performed. MOVE.L (C)
starts in the <ea> calculate requesting an immediate extension word for its effective
address.
passes through the <ea> fetch with no operation performed. The next instruction
starts in the <ea> calculate stage.
effective address.
busy. If the second TRAPF instruction (N2) in the <ea> fetch stage requires an
operand fetch, the write-back for MOVE.L (C) stalls in the write-back stage since it
is a lower priority.
Figure 10-1. Simple Instruction Timing Example
<ea> CALCULATE
WRITE-BACK
<ea> FETCH
Freescale Semiconductor, Inc.
EXECUTE
For More Information On This Product,
LABEL
P1
C1
N1
N2
P1
Go to: www.freescale.com
C
A
B
M68040 USER’S MANUAL
C2
P1
A
TRAPF
MOVE.L
ADDQ.L
MOVE.L
TRAPF
TRAPF
INSTRUCTION
C3
P1
B
A
C4
$1000,D0
#1,D0
D0,$1000
C
B
A
C5
N1
C
B
CALCULATE
C6
N2
N1
C
<ea>
1
1
1
1
1
1
C7
N2
N1
C
EXECUTE
1
1
1
1
1
1
10-5

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