MC68040FE33A Freescale Semiconductor, MC68040FE33A Datasheet - Page 82

• Manufacturer Part Number: MC68040FE33A
• Description: IC MICROPROCESSOR 32BIT 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68040FE33A

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Package: 184CQFP
• Processor Series: M680xx
• Core: CPU32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

3.7 MMU INSTRUCTIONS
The M68040 instruction set includes three privileged instructions that perform MMU
operations. The following paragraphs briefly describe each of these instructions. For
detailed descriptions of these instructions, refer to M68000PR/AD, M68000 Family
Programmer's Reference Manual .
3.7.1 MOVEC
The MOVEC instruction transfers data between an integer data register, or memory
location, and any of the M68040 control and status registers. The operating system uses
the MOVEC instruction to control and monitor MMU operation by manipulating and
reading the eight MMU registers.
3.7.2 PFLUSH
The PFLUSH instruction flushes or invalidates address translation descriptors in the
ATCs. PFLUSHA, a version of the PFLUSH instruction, flushes all entries. The PFLUSH
instruction flushes a user or supervisor entry with a specified logical address. The
PFLUSHAN and PFLUSHN instruction variants qualify entry selection further by flushing
only entries that are nonglobal, indicated by a cleared G-bit in the entry.
3.7.3 PTEST
The PTEST instruction performs a table search operation for a specified function code and
logical address and sets the appropriate bit fields in the MMUSR to indicate conditions
encountered during the search. PTEST automatically flushes the corresponding entry from
the cache before searching the tables and loads the latest information from the translation
tables into the ATC. The exception routines of the operating system can use this
instruction to identify MMU faults.
PTEST is primarily used in access error exception handlers. For example, if a bus error
has occurred, the handler can execute an instruction sequence such as the following
sequence:
The transfer modifier field copied into the destination function code (DFC) register
indicates whether the faulted access was a supervisor or user mode access and whether
it was an instruction prefetch or data access. The PTEST instruction uses the DFC value
to determine which translation table (supervisor or user) to search and which ATC (data or
instruction) to create the entry in. After executing this code sequence, the handler can
examine the MMUSR for the source of the fault.
The M68040 MMU instructions use opcodes that are different from those for the
corresponding instructions in the MC68030 and MC68851. All MMU opcodes for the
MOTOROLA
MOVE.B (A7,offset1),D0
MOVEC D0,DFC
MOVEA.L (A7,offset2),A0
PTESTW (A0)
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M68040 USER'S MANUAL
into DFC register
Copy fault address from stack frame into address register
Test address in A0 with function code in DFC registers
Copy transfer modifier field from stack frame
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