PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 92
PEB20534H-10V2.1
Manufacturer Part Number
PEB20534H-10V2.1
Description
Communication Controller 208-Pin FQFP
Manufacturer
Infineon Technologies
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5.2.3
The central receive FIFO is shared by all 4 receive channels and dynamically allocated
to the SCCs. One central receive FIFO threshold controls data transfer to the host
memory.
Figure 21
Mention, that the SCCs typically forward receive data in portions of 15 DWORDs to the
central receive FIFO. These coherent data portions are a precondition for PCI burst
transactions.
Data Sheet
Central Receive FIFO (RFIFO)
Central Receive FIFO Threshold
128 DWORDs
128
Receive data transferred
1
to shared memory
receive FIFO
SCC0
0
92
1
2
3
Receive FIFO Threshold:
FIFOCR3.RFTHRESH
watermark = TFRTHRESH*Mx
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
2000-05-30
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