UPD42S18165LG5-A60-7JF NEC, UPD42S18165LG5-A60-7JF Datasheet

no-image

UPD42S18165LG5-A60-7JF

Manufacturer Part Number
UPD42S18165LG5-A60-7JF
Description
UPD42S18165LG5-A60-7JF3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, EDO, BYTE READ/WRITE MODE
Manufacturer
NEC
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD42S18165LG5-A60-7JF
Manufacturer:
SEK
Quantity:
12 500
Part Number:
UPD42S18165LG5-A60-7JF
Manufacturer:
NEC
Quantity:
633
Part Number:
UPD42S18165LG5-A60-7JF/US
Manufacturer:
NEC
Quantity:
3 476
Document No. M10562EJ8V0DS00 (8th edition)
Date Published January 1997 N
Printed in Japan
Description
Features
• EDO (Hyper page mode)
• 1,048,576 words by 16 bits organization
• Single +3.3 V 0.3 V power supply
• Fast access and cycle time
• The PD42S18165L can execute CAS before RAS self refresh
PD42S18165L-A50, 4218165L-A50
PD42S18165L-A60, 4218165L-A60
PD42S18165L-A70, 4218165L-A70
PD42S18165L
PD4218165L
The PD42S18165L, 4218165L are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional EDO.
EDO is a kind of the page mode and is useful for the read operation.
Besides, the PD42S18165L can execute CAS before RAS self refresh.
The PD42S18165L, 4218165L are packaged in 50-pin plastic TSOP (II) and 42-pin plastic SOJ.
Part number
Part number
1 M-WORD BY 16-BIT, EDO, BYTE READ/WRITE MODE
1,024 cycles/128 ms
1,024 cycles/16 ms
3.3 V OPERATION 16 M-BIT DYNAMIC RAM
Refresh cycle
The information in this document is subject to change without notice.
PD42S18165L, 4218165L
Power consumption
Active (MAX.)
612 mW
540 mW
504 mW
The mark
DATA SHEET
CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh
CAS before RAS refresh,
RAS only refresh,
Hidden refresh
shows major revised points.
Access time
Refresh
(MAX.)
50 ns
60 ns
70 ns
MOS INTEGRATED CIRCUIT
R/W cycle time
104 ns
124 ns
(MIN.)
84 ns
Power consumption at standby
(CMOS level input)
(CMOS level input)
EDO (Hyper page mode)
cycle time (MIN.)
0.54 mW
1.8 mW
(MAX.)
20 ns
25 ns
30 ns
©
1995

UPD42S18165LG5-A60-7JF Summary of contents

Page 1

V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, EDO, BYTE READ/WRITE MODE Description The PD42S18165L, 4218165L are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional EDO. EDO is a kind of the page mode and ...

Page 2

Ordering Information Access time Part number (MAX.) PD42S18165LG5-A50-7JF 50 ns PD42S18165LG5-A60-7JF 60 ns PD42S18165LG5-A70-7JF 70 ns PD42S18165LLE-A50 50 ns PD42S18165LLE-A60 60 ns PD42S18165LLE-A70 70 ns PD4218165LG5-A50-7JF 50 ns PD4218165LG5-A60-7JF 60 ns PD4218165LG5-A70-7JF 70 ns PD4218165LLE-A50 50 ns PD4218165LLE-A60 60 ns ...

Page 3

... Address Inputs I/O1 to I/O16 : Data Inputs/Outputs RAS : Row Address Strobe UCAS : Column Address Strobe (upper) LCAS : Column Address Strobe (lower Write Enable OE : Output Enable V : Power Supply CC GND : Ground Connection PD42S18165L, 4218165L 42-pin Plastic SOJ (400 mil) GND I/O16 I/O1 2 I/O15 I/O2 3 I/O14 I/O3 4 I/O13 I/O4 5 ...

Page 4

Block Diagram RAS LCAS Clock Generator UCAS CAS before GND RAS Counter Row Address Buffer Column Address Buffer PD42S18165L, 4218165L Lower Byte Control Data Output Upper Buffer ...

Page 5

... It also selects the following function. • CAS before RAS refresh CAS activates data input/output circuit by latching column address and selecting a digit line connected with the sense amplifier. Address bus. Input total 20-bit of address signal, upper 10-bit and lower 10-bit in sequence (address multiplex method). ...

Page 6

Hyper Page Mode (EDO) The hyper page mode (EDO kind of page mode with enhanced features. The two major features of the hyper page mode (EDO) are as follows. 1. Data output time is extended. In the hyper ...

Page 7

... Cautions when using the hyper page mode (EDO) 1. CAS access should be used to operate make I/Os to Hi-Z in read cycle necessary to control RAS, CAS, WE follows. The effective specification depends on the state of each signal. (1) Both RAS and CAS are inactive (at the end of read cycle) ...

Page 8

Electrical Specifications • CAS means UCAS and LCAS. • All voltages are referenced to GND. • After power wait more than 100 s (RAS, CAS inactive) and then, execute eight CAS CC CC(MIN.) before RAS or ...

Page 9

DC Characteristics (Recommended operating conditions unless otherwise noted) Parameter Symbol Operating current I CC1 Standby PD42S18165L I CC2 current PD4218165L RAS only refresh current I CC3 Operating current I CC4 (Hyper page mode (EDO)) CAS before RAS I CC5 refresh ...

Page 10

AC Characteristics (Recommended Operating Conditions unless otherwise noted) AC Characteristics Test Conditions (1) Input timing specification (MIN 0 (MAX (3) Output load condition V CC 1,180 ...

Page 11

Notes 1. In CAS before RAS refresh cycles < t < 100 s, RAS precharge time for CAS before RAS self refresh (t RAS 2. For read cycles, access time is defined as follows: Input conditions ...

Page 12

Write Cycle Parameter WE hold time referenced to CAS WE pulse width WE lead time referenced to RAS WE lead time referenced to CAS WE setup time OE hold time Data-in setup time Data-in hold time Notes ...

Page 13

... OFR (MAX.) WEZ (MAX.) not referenced make I/Os to Hi-Z in read cycle necessary to control RAS, CAS, WE follows. The effective specification depends on state of each signal. (1) Both RAS and CAS are inactive (at the end of the read cycle) WE: inactive, OE: active t is effective when RAS is inactivated before CAS is inactivated ...

Page 14

Refresh Cycle Parameter CAS setup time CAS hold time (CAS before RAS refresh) RAS precharge CAS hold time RAS pulse width (CAS before RAS self refresh) RAS precharge time (CAS before RAS self refresh) CAS hold time (CAS before RAS ...

Page 15

Read Cycle V – IH RAS V – CRP V UCAS – – LCAS IL t RAD t t ASR RAH V – IH Address Row V – – – IL ...

Page 16

Upper Byte Read Cycle V – IH RAS V – CRP V – IH UCAS V – CRP V – IH LCAS V – RAD t t ASR RAH V – IH Address Row ...

Page 17

Lower Byte Read Cycle V – IH RAS V – CRP V – IH UCAS V – CRP V – IH LCAS V – ASR RAH V – IH Address Row V ...

Page 18

Early Write Cycle V IH– RAS V IL– t CRP UCAS V IH– LCAS V IL– t RAD t t ASR RAH V IH– Address Row V IL– V IH– IL– U I/O V IH– L I/O V ...

Page 19

Upper Byte Early Write Cycle V – IH RAS V – CRP V – IH UCAS V – CRP V – IH LCAS V – RAD t t ASR RAH V – IH Address ...

Page 20

Lower Byte Early Write Cycle V – IH RAS V – CRP V – IH UCAS V – CRP V – IH LCAS V – RAD t t ASR RAH V – IH Address ...

Page 21

Late Write Cycle V IH– RAS V IL– t CRP V UCAS IH– V LCAS IL– t RAD t t ASR RAH V IH– Address Row V IL– V IH– IL– V IH– IL– t OED ...

Page 22

Upper Byte Late Write Cycle V – IH RAS V – CRP V – IH UCAS V – CRP V – IH LCAS V – RAD t t ASR RAH V – IH Address ...

Page 23

Lower Byte Late Write Cycle V – IH RAS V – CRP V – IH UCAS V – CRP V – IH LCAS V – RAD t t ASR RAH V – IH Address ...

Page 24

Read Modify Write Cycle V IH– RAS V IL– CRP RCD V IH– UCAS V IL– LCAS t RAD ASR RAH V IH– Address Row V IL– V IH– IL– V IH– OE ...

Page 25

Upper Byte Read Modify Write Cycle V – IH RAS V – CRP V – IH UCAS V – CRP V – IH LCAS V – RAD t t ASR RAH V – IH ...

Page 26

Lower Byte Read Modify Write Cycle V – IH RAS V – CRP V – IH UCAS V – CRP V – IH LCAS V – RAD t t ASR RAH V – IH ...

Page 27

Hyper Page Mode (EDO) Read Cycle V – IH RAS V – CRP RCD V UCAS – LCAS – RAD ASR RAH ASC V – IH Address Row V – ...

Page 28

Hyper Page Mode (EDO) Byte Read Cycle V – IH RAS V – CSH t CRP t RCD V – IH UCAS V – CRP V – IH LCAS V – RAD t t ...

Page 29

Hyper Page Mode (EDO) Read Cycle (WE Control) V – IH RAS V – CRP RCD V – UCAS IH V – LCAS IL t RAD ASR RAH ASC V – IH Address Row ...

Page 30

Hyper Page Mode (EDO) Read Cycle (OE Control) V – IH RAS V – CSH t t CRP RCD V – UCAS IH V LCAS – RAD RAH ASR ASC V – IH ...

Page 31

Hyper Page Mode (EDO) Early Write Cycle V IH– RAS V IL– t CSH t t CRP RCD V UCAS IH– V LCAS IL– t RAD ASR RAH ASC V IH– Address Row Col. V IL– t ...

Page 32

Hyper Page Mode (EDO) Byte Early Write Cycle V IH– RAS V IL– t CSH t CRP t RCD V IH– UCAS V IL– t CRP V IH– LCAS V IL– t RAD RAH ASR ASC V ...

Page 33

Hyper Page Mode (EDO) Late Write Cycle V IH– RAS V IL– t CSH t t CRP RCD V UCAS IH– V LCAS IL– t RAD ASR RAH ASC V IH– Address Row Col. V IL– t ...

Page 34

Hyper Page Mode (EDO) Byte Late Write Cycle V IH– RAS V IL– t CSH t CRP t RCD V IH– UCAS V IL– t CRP V IH– LCAS V IL– t RAD ASR RAH ASC V ...

Page 35

Hyper Page Mode (EDO) Read Modify Write Cycle V IH– RAS V IL– CRP RCD V IH– UCAS V IL– LCAS t RAD ASR RAH ASC CAH V IH– Address Row Col. V IL– ...

Page 36

Hyper Page Mode (EDO) Byte Read Modify Write Cycle V IH– RAS V IL– t CRP t RCD V IH– UCAS V IL– t CRP V IH– LCAS V IL– t RAD CAH ASR RAH ASC ...

Page 37

Hyper Page Mode (EDO) Read and Write Cycle V – IH RAS V – CRP RCD V – UCAS IH V – LCAS IL t RAD ASR RAH ASC V – IH Address Row ...

Page 38

CAS Before RAS Self Refresh Cycle (Only for the PD42S18165L) V – IH RAS V – CSR UCAS V – – LCAS IL Remark Address, WE, OE: Don’t care Cautions on Use of CAS Before RAS ...

Page 39

CAS Before RAS Refresh Cycle V IH– RAS V IL– CSR CHR V UCAS IH– LCAS V IL– Remark Address, WE, OE: Don’t care RAS Only Refresh Cycle V IH– RAS V IL– t CRP V UCAS IH– ...

Page 40

Hidden Refresh Cycle (Read) V – IH RAS V – CRP V UCAS – IH LCAS V – RAD t t ASR RAH V – IH Address Row V – – ...

Page 41

Hidden Refresh Cycle (Write) V IH– RAS V IL– CRP RCD V UCAS IH– V LCAS IL– t RAD t t ASR RAH V IH– Address Row V IL– V IH– IL– I/O IH– ...

Page 42

Package Drawings 50PIN PLASTIC TSOP(II) (400 mil NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition ...

Page 43

PIN PLASTIC SOJ (400 mil NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. PD42S18165L, 4218165L ...

Page 44

Recommended Soldering Conditions The following conditions (see tables below and next page) must be met for soldering conditions of the PD42S18165L, 4218165L. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales ...

Page 45

PD42S18165LLE, 4218165LLE: 42-pin plastic SOJ (400 mil) Soldering process Infrared ray reflow Peak temperature of package surface: 235 C or lower, Reflow time: 30 seconds or less (210 C or higher), Number of reflow processes: MAX. 3 Exposure limit: 7 ...

Page 46

PD42S18165L, 4218165L ...

Page 47

... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...

Page 48

... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...

Related keywords