AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet

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AT32UC3A3128

Manufacturer Part Number
AT32UC3A3128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A3128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Feature Summary
Small area, high clock frequency.
32-bit load/store AVR32A RISC architecture.
15 general-purpose 32-bit registers.
32-bit Stack Pointer, Program Counter and Link Register reside in register file.
Fully orthogonal instruction set.
Pipelined architecture allows one instruction per clock cycle for most instructions.
Byte, half-word, word and double word memory access.
Fast interrupts and multiple interrupt priority levels.
Privileged and unprivileged modes enabling efficient and secure Operating Systems.
Optional MPU allows for operating systems with memory protection.
Innovative instruction set together with variable instruction length ensuring industry
leading code density.
DSP extention with saturating arithmetic, and a wide variety of multiply instructions.
Memory Read-Modify-Write instructions.
Optional advanced On-Chip Debug system.
FlashVault
nontrusted code on the same CPU.
Optional floating-point hardware.
support through Secure state for executing trusted code alongside
AVR32UC
Technical
Reference
Manual
32002F–03/2010

Related parts for AT32UC3A3128

AT32UC3A3128 Summary of contents

Page 1

Feature Summary • Small area, high clock frequency. • 32-bit load/store AVR32A RISC architecture. • 15 general-purpose 32-bit registers. • 32-bit Stack Pointer, Program Counter and Link Register reside in register file. • Fully orthogonal instruction set. • Pipelined architecture ...

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Introduction AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code den- sity. In addition, the instruction set architecture has been tuned to allow for ...

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Load/store to an address specified by a small immediate (direct addressing within a small page) • Load/store to an address specified by a pointer register and an index register. The register file is organized as 16 32-bit registers and ...

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Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler ...

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Figure 1-1. Instruction memory controller 1.8 AVR32UC CPU revisions Three revisions of the AVR32UC CPU currently exist: • Revision 1 implementing revision 1 of the AVR32 architecture. • Revision 2 implementing revision 2 of the AVR32 architecture, and with a ...

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Floating-point instructions as described in Revision 3 of the AVR32UC CPU added the following system registers: • SS_STATUS • SS_ADRF, SS_ADRR, SS_ADR0, SS_ADR1 • SS_SP_SYS, SS_SP_APP • SS_RAR, SS_RSR Revision 3 of the AVR32UC CPU ...

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Programming Model This chapter describes the programming model and the set of registers accessible to the user. It also describes the implementation options in AVR32UC. 2.1 Architectural compatibility AVR32UC is fully compatible with the Atmel AVR32A architecture. AVR32UC devices ...

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Figure 2- lic a tio ...

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Figure 2-3. Bit Secure State This bit is indicates if the processor is executing in the secure state. Only implemented in devices implementing revision 3 of the AVR32 architecture, set ...

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Table 2- Exception mask When this bit is set, exceptions are masked. Exceptions are enabled otherwise. The bit is auto- matically set when exception processing is initiated or Debug Mode is entered. Software may clear this bit ...

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T - Scratch bit This bit is not set or cleared implicit by any instruction and the programmer can therefore use this bit as a custom flag to for example signal events in the program. This bit is cleared at ...

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Table 2-2. Reg # 33- ...

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Table 2-2. Reg # 100 101 102 103 104 105 106 107 108 109 ...

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Table 2-2. Reg # 110 111 112-191 192-255 248 249 250 251 252 253 254 255 SR- Status Register The Status Register is mapped into the system register space. This allows loaded into the register file to ...

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Table 2-3. Name SPL CPL COP SIE ECR - Exception Cause Register This register identifies the cause of the most recently executed exception. This information may be used to handle exceptions more efficiently in certain operating systems. The register is ...

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COMPARE - Cycle Counter Compare Register Used together with COUNT to implement a periodic interrupt for example for an OS timer. The contents and functionality of this register is described in detail in COUNT registers” on page BEAR - Bus ...

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MSU_ADDRHI, MSU_ADDRLO, MSU_LENGTH, MSU_CTRL, MSU_STATUS, MSU_DATA, MSU_TAIL - Memory Service Unit Registers These registers are system register mappings of the Memory Service Unit Registers. Refer to Section 9.8 ”Memory Service Unit” on page 138 2.6 COMPARE and COUNT registers The ...

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Table 2-4 on page 18 Table 2-4. Name Processor ID RESERVED Processor revision AT AR MMUT 32002F–03/2010 shows the CONFIG0 fields. CONFIG0 Fields Bit Description Specifies the type of processor. This allows the application to 31:24 distinguish ...

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Table 2-4. Name Table 2-5 on page 19 Table 2-5. Name IMMU SZ DMMU SZ ISET ILSZ IASS DSET DLSZ DASS 32002F–03/2010 CONFIG0 Fields (Continued) Bit Description On-Chip Debug implemented Value Semantic OCD ...

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Pipeline 3.1 Overview AVR32UC is a pipelined processor with three pipeline stages: IF, ID and EX. All instructions are issued and complete in order. Some instructions may require several iterations through the EX stage in order to complete. The ...

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EX pipeline stage The Execute (EX) pipeline stage performs register file reads, operations on registers and mem- ory, and register file writes. 3.4.1 ALU section The ALU pipeline performs most of the data manipulation instructions, like arithmetical and logi- ...

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The read-modify-write instructions memc, mems and memt are performed as a non-interruptable sequence of read from and write to memory. The load-store section generates the control sig- nals required to perform this sequence. This sequence takes several clock cycles, so ...

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The same mechanisms are used to service all different types of events, including external inter- rupt requests, yielding a uniform event handling scheme. Each pipeline stage has a pipeline register that holds the exception requests associated with the instruction in ...

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Supervisor calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism ...

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This can usually be ensured by scheduling the code sequence disasserting the interrupt request in such a way that one can be certain that the interrupt request has actually been disasserted before the rete instruction is executed. Code 3-1. // ...

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Many peripheral modules that are able to assert interrupt requests have control registers or other means of masking one or more of its interrupt requests. For example, a USART can con- tain an interrupt mask register with individual bits for ...

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If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 3-4. If events occur on several instructions at different locations in the pipeline, the events on the oldest ...

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Table 3-4. Priority and handler addresses for events Priority Handler Address 1 0x8000_0000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...

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PC = 0x8000_0000; All other system registers are reset to their reset value, which may or may not be defined. Refer to the Programming Model chapter for details. 3.9.1.2 OCD Stop CPU Exception The OCD Stop CPU exception is generated ...

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The exception handler is responsible for performing the appropriate action. *(--SP *(--SP SR[M2:M0] = B’110; SR[EM SR[GM EVBA | 0x08; BEAR = failing address 3.9.1.6 Bus Error Exception on Instruction Fetch ...

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Since the INT3 exception is unrelated to the instruction stream, the instructions in the pipeline are allowed to complete. After finishing the INT3 exception routine, execution should continue at the instruction following the last completed instruction in the instruction stream. ...

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SR[I1M] bit when accepting an INT1 exception, inhibiting new INT1 requests when process- ing an INT1 request. The INT1 Exception handler address is calculated by adding EVBA to an interrupt vector offset specified by an interrupt controller outside the ...

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Instruction Address Exception The Instruction Address Error exception is generated if the generated instruction memory address has an illegal alignment. *(--SP *(--SP SR[M2:M0] = B’110; SR[EM SR[GM EVBA | 0x14; 3.9.1.13 ITLB Miss ...

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PC = EVBA | 0x1C; 3.9.1.16 Illegal Opcode This exception is issued when the core fetches an unknown instruction, or when a coprocessor instruction is not acknowledged. When entering the exception routine, the return address on stack points to the ...

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Data Read Address Exception The Data Read Address Error exception is generated if the address of a data memory read has an illegal alignment. *(--SP *(--SP SR[M2:M0] = B’110; SR[EM SR[GM EVBA | ...

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SR[M2:M0] = B’110; SR[EM SR[GM EVBA | 0x3C; 3.9.1.23 DTLB Write Protection Exception The DTLB Protection exception is generated when the data memory write violates the access rights specified by the protection region in ...

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Floating-point Exception Unused in AVR32UC. 3.9.1.27 Coprocessor Absent Exception The Coprocessor Absent exception is generated when a nonexisting coprocessor is addressed by a coprocessor instruction. Used only if one or more coprocessors are present. Executing coprocessor instructions in systems ...

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Note that the overall system latency from an interrupt request is signaled to the request is being handled depends on a number of things in addition to the latency through the CPU. The latency through the interrupt controller will affect ...

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The maximum NMI latency can be calculated as follows: Table 3-10. Source Wait for the slowest instruction to complete Stack return address and status register, and jump to autovector target Wait for autovector target instruction to be fetched TOTAL 32002F–03/2010 ...

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Floating Point Hardware Newer versions of UC3 CPU introduced optional floating-point hardware performing 32-bit float- ing-point operations. Instructions controlling this hardware are mapped into the coprocessor instruction space, addressed as coprocessor 0. The CONFIG0 system register F bit indicates ...

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The following mapping from floating point compare results to AVR32 status register flags is used: Table 4-1. Compare result Less Greater Equal Unordered Table 4-2. Branch if: Equal Not Equal Greater than or ...

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Instruction set The following instructions are provided: Table 4-3. Mnemonics fmac.s fnmac.s fmsc.s fnmsc.s fmul.s fnmul.s fadd.s fsub.s : Table 4-4. Mnemonics fcastrs.sw fcastrs.uw fcastsw.s fcastuw.s 32002F–03/2010 Floating point arithmetical instructions Operands Description Multiply accumulate. Rd, Ra, Rx, Ry ...

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Table 4-5. Mnemonics fcp.s fchk.s : Table 4-6. Mnemonics frcpa.s frsqrta.s 4.4 Detailed instruction description 32002F–03/2010 Floating point compare instructions Operands Description Compare floating point values in Rd and Rx, Rd, Rx and set status register flags accordingly. Check ...

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FMAC.S – Floating Point Multiply-Accumulate Description Performs multiply-accumulate of the registers specified and stores the result in destination regis- ter. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32002F–03/2010 Rd ← Rx*Ry; fmac.s ...

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FNMAC.S – Floating Point Negate-Multiply-Accumulate Description Performs negate-multiply-accumulate of the registers specified and stores the result in destina- tion register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32002F–03/2010 Rd ← Rx*Ry; ...

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FMSC.S – Floating Point Multiply-Subtract Description Performs multiply-subtract of the registers specified and stores the result in destination register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32002F–03/2010 Rd ← Rx*Ry; fmsc.s Rd, ...

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FNMSC.S – Floating Point Negate-Multiply-Subtract Description Performs negate-multiply-subtract of the registers specified and stores the result in destination register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32002F–03/2010 Rd ← Rx*Ry; fnmsc.s ...

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FADD.S – Floating Point Add Description Performs addition of the registers specified and stores the result in destination register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32002F–03/2010 Rd ← Ry; fadd.s Rd, ...

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FSUB.S – Floating Point Subtract Description Performs subtraction of the registers specified and stores the result in destination register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32002F–03/2010 Rd ← Ry; fsub.s Rd, ...

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FMUL.S – Floating Point Multiplication Description Performs multiplication of the registers specified and stores the result in destination register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32002F–03/2010 Rd ← Ry; fmul.s Rd, ...

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FNMUL.S – Floating Point Multiply-Negate Description Performs multiply-negate of the registers specified and stores the result in destination register. Operation: I. Syntax: I. Operands: I. Status Flags: Opcode 32002F–03/2010 Rd ← Ry; fnmul.s ...

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FCAST{S,U}W.S – Convert from Integer to Floating Point Description Converts the signed or unsigned integer specified and stores the result in destination register. The conversion used is rounds to nearest, ties to even. Operation: I. II. Syntax: I. II. Operands: ...

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FCASTRS.{S,U}W – Convert from Floating Point to Integer Description Converts the floating-point number in the specified register to a signed or unsigned integer and stores the result in destination register. Rounding used is towards zero. Operation: I. II. Syntax: I. ...

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FCP.S – Floating Point Compare Description Performs a compare between the two floating point operands specified. The operation is imple- mented by doing a floating-point subtraction without writeback of the difference. The operation sets the status flags according to the ...

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FCHK.S – Floating Point Check for Special Values Description Checks the floating point operand specified for the special values Infinity, Not-a-Number and Denormal. A check is also performed for values with the two biggest possible representable exponents, i.e. 0xFD and ...

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Opcode 32002F–03/2010 AVR32 ...

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FRCPA.S – Floating Point Reciprocal Approximation Description Returns an approximation of the reciprocal of the operand. This can be used as a starting point for iterative approximation algorithms. Also checks the operand for the special values Infinity, Not-a-Number and Denormal. ...

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FRSQRTA.S – Floating Point Reciprocal Square Root Approximation Description Returns an approximation of the reciprocal of the square root of the operand. This can be used as a starting point for iterative approximation algorithms. Also checks the operand for the ...

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Secure State Revision 3 of the AVR32 architecture introduced a separate system state allowing execution of secure or secret code alongside nonsecure code on the same processor. The secret code will execute in the secure state, and therefore be ...

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Figure 5-1. Typical secure state use scenario Empty device ATMEL 5.3 Secure state boot sequence At system boot time, hardware state machines preloads the secure state address registers with an initial value programmed into a secure section in the flash. ...

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Memory System AVR32UC implements a 32-bit unsegmented memory space. Regions of this memory space can be protected by an optional MPU. The memory map is as follows: Figure 6-1. 6.1 Memory sections The memory map contains four sections, named ...

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Memory interfaces The AVR32UC CPU has three memory interfaces: • IF stage HSB master interface for instruction fetches • EX stage HSB master interface for data accesses into BOOT or HSB sections • EX stage HSB slave interface enabling ...

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RAMs when the current owner voluntarily releases the RAMs, or after the SPL/CPL timeout period, whichever comes first. If the CPU wins arbitration for the RAMs, the CPU is guaranteed to own the RAM for the period ...

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Refer to the device datasheet for information on any relationships between CPU and device clock frequencies imposed by the local bus. 6.5 IRAM Write buffer The EX stage has a write buffer used to hold data to be ...

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In some cases, this may lead to UNPREDICTABLE behavior in the system. One example of this is ...

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Memory Protection Unit The AVR32 architecture defines an optional Memory Protection Unit (MPU). This is a simpler alternative to a full MMU, while at the same time allowing memory protection. The MPU allows the user to divide the memory ...

Page 67

Register space, their addresses are presented in accessed with the mtsr and mfsr instructions. The MPU interface registers are shown below. The suffix n can have the range 0-7, indicating which region the register is associated with. Figure 7-1. ...

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Size - Size of the protection region. The possible sizes are shown in Table 7-1. Size B’00000 to B’01010 B’01011 B’01100 B’01101 B’01110 B’01111 B’10000 B’10001 B’10010 B’10011 B’10100 B’10101 B’10110 B’10111 B’11000 B’11001 B’11010 B’11011 B’11100 B’11101 B’11110 ...

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MPU Cacheable Register MPUCRA / MPUCRB The MPUCR registers have one bit per region, indicating if the region is cacheable. If the corre- sponding bit is set, the region is cacheable. The register is written to ...

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DTLB Protection Violation An DTLB protection violation is issued if a data access violates access permissions. The violat- ing access is not executed. The address of the failing instruction is placed on the system stack. 7.2.2.3 ITLB Miss Violation ...

Page 71

Instruction Cycle Summary This chapter presents the instructions in AVR32UC CPU, and the number of clock cycle they require to complete. All the instructions in each group behave similarly in the pipeline. The final subchapter presents code examples to ...

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CPU revision Revision 1, 2 and 3 of the AVR32UC CPU has the same instruction timings, except that the divider in revision 2 and later is faster than in revision 1. Instructions only present in revision ...

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Table 8-1. sub subhh.w sub{cond4} tnbz and and{cond4} andn andh andl com eor eor{cond4} eorh eorl or or{cond4} 32002F–03/2010 ALU instructions C Rd, Rs Rd, Rx, E (Ry << sa) Subtract. C Rd, imm E Rd, imm E Rd, Rs, ...

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Table 8-1. orh orl tst bfins bfexts bfextu bld brev bst casts.b casts.h castu.b castu.h cbr clz sbr swap.b swap.bh swap.h asr lsl lsr rol ror mov mov{cond4} 32002F–03/2010 ALU instructions E Rd, imm Logical OR (High Halfword). E Rd, ...

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Table 8-1. movh csrf csrfcz ssrf sr{cond4} 8.5 Multiply instructions These instructions require one pass through the multiplier array and produce a 32- or 48-bit result. For mulrndhh, a rounding value of 0x8000 is added to the product producing the ...

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MAC instructions These instructions require one pass through the multiplier array and produce a 32- or 48-bit result. This result is added to an accumulator register. A valid copy of this accumulator may be cached in the accumulator cache. ...

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Divide instructions These instructions require several cycles in the EX stage to complete. The divs and divu instruc- tions will be aborted immediately if any interrupts are pending, in order to limit the interrupt latency. The divide instructions are ...

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The stcond instruction takes 2 cycles if the store is not performed, 3 cycles if the store is performed. All issue latencies are given for accesses to IRAM or LOCAL. These timings must be modified as follows for accesses to ...

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Table 8-7. ld.uh ld.uh{cond4} ld.sh ld.sh{cond4} ld.w ld.w{cond4} ld.d ldins.b ldins.h ldswp.sh ldswp.uh ldswp.w lddpc 32002F–03/2010 Load and store instructions C Rd, Rp++ Load unsigned halfword with post-increment. C Rd, --Rp Load unsigned halfword with pre-decrement. C Rd, Rp[disp] Load ...

Page 80

Table 8-7. lddsp st.b st.b{cond4} st.d st.h st.h{cond4} st.w st.w{cond4} stcond stdsp sthh.w stswp.h stswp.w 32002F–03/2010 Load and store instructions C Rd, SP[disp] Load with displacement from SP. C Rp++, Rs Store with post-increment. C --Rp, Rs Store with pre-decrement. ...

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Multiple data memory access instructions These instructions perform multiple data accesses. The incremental accesses are performed as word accesses. The number of cycles is dependent on the number of registers to load or store, n. The issue latency must ...

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Branch instructions The branch instructions cause a pipeline flush and change-of-flow if taken. Two cycles must be added to the issue latency if the branch is taken. Table 8-9. Mnemonics br{cond3} br{cond4} rjmp ret{cond4} 8.13 Call instructions Call instructions ...

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The rete instruction has a latency of 12 cycles when returning from INT0-INT3 modes, 5 cycles otherwise. The rete instruction can be aborted by a pending interrupt. Table 8-11. Mnemonics retd rete rets retss 8.15 Swap instructions The swap instruction ...

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Table 8-14. pref sleep sync 8.18 Read-modify-write instructions This group contains instructions that perform atomical bit-operations on memory addresses. These instructions require multiple cycles inside the memory controller, but these can be per- formed in parallel with subsequent instructions if ...

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All instructions are executed in the precise sequence shown below Instruction add r5, r0 sub r5, r5 ssrf AVR32_SREG_C ssrf AVR32_SREG_GM max r6, r1, r0 mul r5, r1 mac r5, r1 mac r3, r1 mac r3, r1 macs.d r2, ...

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Instruction ldm HSB++, r5, r6, r7, r8 stm HSB, r5, r6, r7, r8 add r6, r5 memc IRAM, 3 st.w IRAM[4], r8 memc IRAM, 3 mul r5, r9 memc HSB, 7 ld.w r4, IRAM[16] memc HSB, 7 sub r7, r4 ...

Page 87

OCD system 9.1 Overview The AVR32 CPU is targeted at a wide range of 32-bit applications. The CPU can be delivered in very different implementations in various ASIC’s, ASSP’s, and standard parts to satisfy require- ments for low-cost as ...

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CPU, which can also be handled in this level. The emulator translates the communication from the host into commands transmitted to the target over the ...

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Transmit Queue Trace and watchpoint messages are inserted into the Transmit Queue (TXQ) before being trans- mitted on the AUX port. This provides some flexibility between the peak rate of trace message generation and the average rate of message ...

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CPU or trace the program flow. This is accomplished through Ownership Trace Messaging, in which the process ID of the running pro- cess is reported at every process switch. The CPU ...

Page 91

Debug Mode is exited by the retd instruction, both in Monitor Mode and OCD Mode. This restores PC from RAR_DBG and SR from RSR_DBG. 9.2.1.2 A typical debug session flow Figure 9-2 shows an example of a typical flow in ...

Page 92

All other exceptions and interrupts are masked by default when entering Monitor Mode, but the monitor code can explicitly unmask interrupts to allow critical interrupts to be serviced while the system is being debugged. The monitor code will typically ...

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Any instruction valid in Monitor Mode is also valid in OCD Mode. Memory operations can be con- ducted without any special synchronization with external hardware. All OCD units can be configured while the CPU executes in OCD Mode, but the ...

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Debug request The debugger may want to stop CPU operation, unrelated to current instruction execution, e.g. if the user presses a "STOP" button in the debug tool GUI. The debugger will then write the Debug Request (DBR) bit in ...

Page 95

Trapping opcode 0x0000 In Flash-based microcontrollers, the opcode 0x0000 can overwrite any other opcode without having to erase and reprogram the Flash. Therefore this instruction can enter Debug Mode, as for the breakpoint instruction. However, the opcode 0x0000 is ...

Page 96

Exceptions and Debug Mode Debug Mode has priority over any execution mode, so that breakpoints can be set in exception and interrupt routines. However breakpoint is set on an instruction which triggers a critical exception, the breakpoint ...

Page 97

Instruction replacement example Table 9-1 shows an example of a code where the user wants to insert a breakpoint. Table 9-1. PC value 0x000010 0x000012 0x000014 0x000016 0x00001A The tool wants to insert a software breakpoint on the instruction ...

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Decrement RAR_DBG in Debug Mode to return to the sleep instruction. This places the CPU back into sleep mode after exiting Debug Mode. 9.2.8 OCD Register Access The OCD registers control the OCD system. Their specification is based on the ...

Page 99

PID and DCCPU can be written. Illegal access to the registers will be ignored with no error reporting. Table 9-3. Register Development Control (DC) Watchpoint Trigger (WT) Data Trace Control (DTC) Data Trace Start Address (DTSA) ...

Page 100

Turn off the interrupt masks in the CPU When an interrupt occurd the CPU will jump to the interrupt handler routine and process the interrupt. The interrupt handler must clear the interrupt before leaving this routing. This is done ...

Page 101

This information is static, and may be used to develop generic Nexus debuggers which will work across a family of AVR32 devices with different Nexus configurations. Table 9-6. R ...

Page 102

Communication Status Register. The emulator should poll the status register and read DCCPU if the dirty bit is set. Table 9-7. R/W R/W 9.2.14.4 Debug Communication Emulator Register (DCEMU) When the emulator writes to this register, a dirty bit is ...

Page 103

Table 9-9. R/W R/W R/W R/W 9.2.14.6 Debug Communication Control Register (DCCR) To enable the DCCPU read and DCEMU dirty interrupts the corresponding enable bits must be set in this register. Table 9-10. R/W R R/W R/W 32002F–03/2010 Debug Communication ...

Page 104

Development Control Register (DC used for basic development control of the CPU. Table 9-11. R/W R/W S R/W R/W R/W R R/W R/W 32002F–03/2010 Development Control Register Bit Number Field Name Init. Val. 31 ABORT 0 30 ...

Page 105

Table 9-11. R/W R/W R/W R/W R R/W R/W R/W 32002F–03/2010 Development Control Register Bit Number Field Name Init. Val. 23 IRP 0 22 SQA 0 21:20 EOS 0 19:14 Reserved 13 DBE 0 12 DBR 0 11:9 Reserved 8 ...

Page 106

Table 9-11. R/W R/W R/W R/W 9.2.14.8 Development Status (DS) register This register is used to examine the debug state of the CPU and the cause for entering Debug Mode. Note that multiple sources may trigger Debug Mode simultaneously, causing ...

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This register is undefined when the CPU is not in Debug Mode. Table 9-12. R 32002F–03/2010 Development Status register Bit Number Field Name Init. Val. 31:29 Reserved 0 28 NTBF ...

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Table 9-12. R 9.2.14.9 Debug Instruction Register (DINST) The Debug Instruction Register contains the instruction to be executed in OCD Mode. The CPU fetches and executes the instruction faster than they can be written by ...

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Debug Program Counter (DPC) This register contains the PC value of the last executed instruction in any non-debug mode. This allows a debugger to sample program execution addresses for statistical purposes without inter- rupting the CPU. If this register ...

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To be able to use JTAG-based debug tools for AVR32 without adapters recommended that a circuit design using an AVR32 device should use a standard 10-pin 50-mil IDC connector with the pinout shown in Table 9-16. The signals ...

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Figure 9-4. 9.3.3 AUX port The Auxiliary (AUX) port and messaging protocol follow the definitions of the Nexus standard. This standard allows varying the number of signalling pins. The following configuration is selected for AVR32UC. • 6 data output pins ...

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The complete signal list of the AUX port is shown in Table 9-18. Table 9-18. Auxiliary pins MCKO MDO MSEO EVTO EVTI RESET_ N 32002F–03/2010 Auxiliary pins Direct Width ion Description Message Clockout (MCKO free-running output clock to ...

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To be able to use AUX-based debug tools for AVR32, a circuit design using an AVR32 device should use a Mictor38 connector (AMP P/N 767054-1) as defined in the Nexus standard, with the pinout shown in Table 9-19. Table 9-19. ...

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Message rules MDO is valid whenever MSEO does not indicate "idle". Fixed length packets are implicitly recognized from the message format, and are not required to end on a port boundary. Thus, packets may also start within a port ...

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Figure 9- ...

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Messages 9.3.4.1 Error The error message indicates various errors that can occur during trace or debugging. Table 9-21 lists the various errors that can be reported, along with the associated ECODE. If trace messages are lost because of insufficient ...

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This includes enabling the AUX port, and controlling the speed of the clock and data compared to the CPU clock. Table 9-22. R R/W R/W R/W R/W R R/W 9.4 Breakpoints 9.4.1 Overview The Nexus ...

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The watchpoint will trigger a Watchpoint Hit message. The OCD system supports up to six program breakpoints modules and two data breakpoint modules. In addition to this, the data trace modules can also be used as data address ...

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Figure 9-7. PC Breakpoint Unit 5 PC Watchpoints 2 Data Watchpoints Trigger Unit Start/ Stop Program Trace Unit 9.4.2 Breakpoint Unit description The Breakpoint unit consists of the units shown in Figure 9-7. The PC Breakpoint Unit (PBU) handles the ...

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The Watchpoint Message Generator (WMG) generates watchpoint messages for all breakpoint modules and data trace watchpoints. Optionally, a breakpoint or watchpoint can be signalled by a pulse on the EVTO pin. This requires DC:EOS bits to be set to 1 ...

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BWA. One data breakpoint module can only compare 32 bits of data. The data ...

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Messages 9.4.5.1 Watchpoint Hit (WH) Table 9-23. Watchpoint Message Packet Size 8 6 9.4.5.2 Trace Watchpoint Hit (TWH) Table 9-24. Trace Watchpoint Message Packet Size 2 6 9.4.6 Registers 9.4.6.1 PC Breakpoint/Watchpoint Address registers (BWA0A, BWA0, BWA1A, BWA1B, BWA2A, ...

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PC Breakpoint/Watchpoint Control registers - (BWC0A, BWC0B, BWC1A, BWC1B, BWC2A, BWC2B) Table 9-26. R 9.4.6.3 Data Breakpoint / Watchpoint Address (BWA3A, BWA3B) Table 9-27. R/W RW 9.4.6.4 Data Breakpoint / Watchpoint Data (BWD3A, ...

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Data Breakpoint / Watchpoint Control (BWC3A, BWC3B) Table 9-29. R R/W R/W 32002F–03/2010 Data Breakpoint / Watchpoint Control (BWC3x) Bit Number Field Name Init. Val. 31:30 BWE 00 29:28 BRW ...

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Watchpoint Trigger Table 9-30. R/W R/W R/W R/W R/W R 9.5 Program trace 9.5.1 Program trace overview The AVR32 OCD system provides program trace support via the debug port. The program trace feature implements a Program Flow Change Model ...

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Program Trace, Indirect Branch messages with sync contain both instruction count and PC, and are transmitted instead of a Program Trace Synchronization message if a syn- chronization condition occurs and the current instruction is a taken direct/indirect branch. 4. ...

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PTSY. In this case, the address of the instruction which generated the branch message can not be explicitly reconstructed from the trace log, but the debugger will normally know which address was returned to when Debug Mode was exited. If ...

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Messages for taken indirect branches and exceptions include how many sequential bytes were executed since the last taken branch or exception, and the unique portion of the branch target address or exception vector address. The unique portion of the branch ...

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ECODE value of 00001 or 00111 immediately prior to the Program Trace Synchroniza- tion Message debug control register field specifies that EVTI pin action is to generate program trace synchronization, and the Event-In (EVTI) pin has been asserted. ...

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The format for indirect branch messages with sync is shown below. The AVR32 OCD system never issues speculative branch messages and there is therefore no CANCEL packet. Table 9-38. Indirect Branch Message with Sync Packet Size (bits ...

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Program Trace Correlation Program Trace Correlation messages are used to correlate events to the program flow that may not be associated with the instruction stream (e.g. Data Trace Messages). The occurrence of an event listed in Table 9-41 will ...

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Using data trace channels as watchpoints Data Trace is enabled for address ranges (trace channels) specified by pairs of Data Trace Start and End Address registers (DTSA/DTEA). Each data access within that boundary will generate an action as specified ...

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Upon exit from a power-down state. This synchronization message is required to allow the unique portion of the data write address of following Data Trace, Data Write Mes- sages to be correctly interpreted by the tool. 4. The Event-In ...

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Data Trace, Data Read with Sync (DTDRS) This message is an alternative to the Data Trace, Data Read Message output instead of a Data Trace, Data Read Message whenever a memory read occurs that matches the debug ...

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Data Trace, Read-Modify-Write (DTRMW) This message is generated when a Read-Modify-Write (RMW) instruction is generated with a target address within an active data trace window. These instructions have the format "memc/s/t imm, bp", and can clear, set, or toggle ...

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Registers 9.6.4.1 Data Trace Control register (DTC) This register controls actions taken on data accesses within all data trace channels. Table 9-49. R/W R/W R/W R R/W R/W 9.6.4.2 Data Trace Start/End Address register (DTSA/DTEA) DTSAn and DTEAn define ...

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Ownership trace information is transmitted out the AUX using an Ownership Trace Message. OTM facilitates ownership trace by ...

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The tool can read and write this register, although it is recommended that only the CPU writes this register. Table 9-53. R/W RW 9.8 Memory Service Unit The Memory Service Unit (MSU) provides access to complex memory operations, such as ...

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Interpreting the results The user should monitor the RESULT register. The possible values are: Table 9-54. Result NOT_IMPL CANCELED BUSY DONE BUS_ERR 9.8.2 NanoTrace The MSU redirect OCD trace output from the normal trace output port to memory. This ...

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DISABLE: The MSU leaves the NanoTrace mode, and goes to idle mode. The OCD system will continue as before, but trace data will go to the trace output port if enabled. • BREAK_STOP: The MSU will ask the OCD ...

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MSU Register summary Table 9-56. Offset 32002F–03/2010 MSU Register Summary Register Address register, high part Address register, low part Length register Control register Status register Data register Tail address register Name Access ...

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Address Register, High Part Name: ADDRHI Access Type: Read/Write Address offset – – – – – – – – • ADDRHI: Address High part Bits 35:32 of full SAB address ...

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Address Register, Low Part Name: ADDRLO Access Type: Read/Write Address offset • ADDRLO: Address Low part Bits 31-2 of full SAB address. • Bits 1:0 Always zero. 32002F–03/2010 29 28 ...

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Length Register Name: LENGTH Access Type: Read/Write Address offset • LENGTH: Length value • Bits 1:0 Always zero. 32002F–03/2010 LENGTH LENGTH ...

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Control Register Name: CTRL Access Type: Read/Write Address offset – – – – – – – – • OP: Requested operation: Table 9-57. OP field of control register OP Name ...

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Status Register Name: STATUS Access Type: Read/Write Address offset – – – – – – – – • RESULT: Result of current or last operation Table 9-59. Result field of ...

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Data Register Name: DATA Access Type: Read/Write Address offset • DATA: Generic Data Register 32002F–03/2010 DATA DATA DATA ...

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Tail Address Register Name: TAIL Access Type: Read/Write Address offset • TAIL: Tail Address Register for NanoTrace buffer. • Bits 1:0 Always zero. 32002F–03/2010 TAIL 21 20 ...

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OCD Message Summary Table 9-60. TCODE 16–26 27 28–32 33 34– 60-62 63 (0x3F) Table 9-62 shows the messages ...

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Table 9-63 shows the format of the transmitted messages. Packets shown in bold are variable length, the others are fixed length. All variable length packets can be truncated by omitting lead- ing zeroes, but will always end on a port ...

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OCD Message Summary Table 9-62. TCODE 16–26 27 28–32 33 34– 60-62 63 (0x3F) Table 9-62 shows the messages ...

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Table 9-63 shows the format of the transmitted messages. Packets shown in bold are variable length, the others are fixed length. All variable length packets can be truncated by omitting lead- ing zeroes, but will always end on a port ...

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OCD Register Summary Use the index shown in the "Register index" column when accessing OCD registers by the Nexus access mechanism (see "mtdr/mfdr index" column when accessing OCD registers by mtdr/mfdr instructions from the CPU (see plied by 4. ...

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Table 9-64. Register Index 40– 74-75 76 77– 255 32002F–03/2010 OCD Register Summary mtdr/mf dr index Register 136 PC Breakpoint/Watchpoint Address 2A (BWA2A) 140 ...

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Revision History Doc. Rev. Date Comments 32002F 2010-03-12 Improved description of events and priority. Replaced invalid reference in the OCD.PDBG register. Note added about overall system interrupt latency. Added MSU system registers. 32002E 2009-09-01 Added Floating-Point hardware description. 32002D ...

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Table of contents 1 Introduction .............................................................................................. 2 2 Programming Model ................................................................................ 7 3 Pipeline ................................................................................................... 20 4 Floating Point Hardware ........................................................................ 40 32002F–03/2010 1.1The AVR family .........................................................................................................2 1.2 The AVR32 Microprocessor Architecture .................................................................2 1.3Exceptions and Interrupts ..........................................................................................3 1.4Java Support .............................................................................................................3 ...

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Secure State ........................................................................................... 59 6 Memory System ..................................................................................... 61 7 Memory Protection Unit ........................................................................ 66 8 Instruction Cycle Summary .................................................................. 71 32002F–03/2010 4.4Detailed instruction description ...............................................................................43 5.1Basic concept ..........................................................................................................59 5.2Typical use scenario ................................................................................................59 5.3Secure state boot sequence ....................................................................................60 5.4Secure ...

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OCD system ............................................................................................ 87 10 Revision History ................................................................................... 155 32002F–03/2010 8.17System control instructions ...................................................................................83 8.18Read-modify-write instructions ..............................................................................84 8.19Code example .......................................................................................................84 9.1Overview .................................................................................................................87 9.2CPU Development Support .....................................................................................90 9.3Debug Port ............................................................................................................109 9.4Breakpoints ...........................................................................................................117 9.5Program trace ........................................................................................................125 9.6Data Trace .............................................................................................................131 9.7Ownership Trace ...

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