AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet
AT32UC3A3128
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AT32UC3A3128 Summary of contents
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... Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro – IDE Interface • One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S, AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S – 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications – Buffer Encryption/Decryption Capabilities • ...
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Support for SPI and LIN – Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line • Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals • One Synchronous Serial Protocol Controller – Supports I2S and ...
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Description The AT32UC3A3/ complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66MHz. AVR32 high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on ...
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Overview 2.1 Block Diagram Figure 2-1. TCK TDO INTERFACE TDI TMS MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N USB_VBIAS USB_VBUS DMFS, DMHS DPFS, DPHS INTERFACE ID VBOF 32KB RAM 32KB RAM DMACA AES CLK CMD[1..0] DATA[15.. EXTINT[7..0] ...
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Configuration Summary The table below lists all AT32UC3A3/A4 memory and package configurations: Table 2-1. Feature Flash SRAM HSB RAM EBI GPIO External Interrupts TWI USART Peripheral DMA Channels Generic DMA Channels SPI MCI slots High Speed USB AES (S ...
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Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multi- plexing on I/O Line section. Figure 3-1. TFBGA144 Pinout (top view PX40 PB00 PA28 B PX10 PB11 ...
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Figure 3-2. LQFP144 Pinout PA21 109 PA22 110 PA23 111 PA24 112 PA20 113 PA19 114 PA18 115 PA17 116 GNDANA 117 VDDANA 118 PA25 119 PA26 120 PB05 121 PA00 122 PA01 123 PA05 124 PA03 125 PA04 126 ...
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Figure 3-3. VFBGA100 Pinout (top view PA28 PA27 B PB00 PB01 C PB11 PA31 D PX12 PX10 E PA02/ GNDIO (1) PX47 F PX19/ VDDIO (1) PX59 G PX05 PX01 H PX04 PX21 J PX03 PX24 K ...
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Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing G ...
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Table 3-1. GPIO Controller Function Multiplexing G P BGA QFP BGA I 144 144 100 PIN PA28 PA29 PA30 PA31 ...
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Table 3-1. GPIO Controller Function Multiplexing G P BGA QFP BGA I 144 144 100 PIN O ( PX14 65 ( PX15 66 ( PX16 67 ( J10 PX17 ...
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Table 3-1. GPIO Controller Function Multiplexing G P BGA QFP BGA I 144 144 100 PIN PX52 103 ( PX53 104 E3 46 PX54 105 J5 79 PX55 106 J4 78 PX56 107 H4 ...
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TFBGA144 Note: 3.2.4 JTAG port connections Table 3-4. TFBGA144 K12 L12 J11 J10 3.2.5 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irre- spective of ...
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Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-6. Signal Description List Signal Name Function VDDIO I/O Power Supply VDDANA Analog Power Supply VDDIN Voltage Regulator Input Supply VDDCORE Voltage Regulator Output for ...
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Table 3-6. Signal Description List Signal Name Function RESET_N Reset Pin DMAACK[1:0] DMA Acknowledge DMARQ[1:0] DMA Requests EXTINT[7:0] External Interrupt Pins SCAN[7:0] Keypad Scan Pins NMI Non-Maskable Interrupt Pin General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] Parallel ...
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Table 3-6. Signal Description List Signal Name Function SDA10 SDRAM Address 10 Line SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDWE SDRAM Write Enable CLK Multimedia Card Clock CMD[1:0] Multimedia Card Command DATA[15:0] Multimedia Card Data SCLK Memory Stick Clock ...
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Table 3-6. Signal Description List Signal Name Function B0 Channel 0 Line B B1 Channel 1 Line B B2 Channel 2 Line B CLK0 Channel 0 External Clock Input CLK1 Channel 1 External Clock Input CLK2 Channel 2 External Clock ...
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Table 3-6. Signal Description List Signal Name Function DMHS USB High Speed Data - DPHS USB High Speed Data + USB_VBIAS USB VBIAS reference USB_VBUS USB VBUS signal VBOF USB VBUS on/off bus power control port ID ID Pin fo ...
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I/O Line Considerations 3.4.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven VDDIO, and has no pull-up resistor. 3.4.2 RESET_N Pin The RESET_N pin is a schmitt input and ...
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Power Considerations 3.5.1 Power Supplies The AT32UC3A3 has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 3.3V nominal • VDDANA: Powers the ADC. Voltage is 3.3V nominal • VDDIN: Input voltage for the voltage ...
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Processor and Architecture Rev: 1.4.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...
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The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some ...
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Figure 4-1. 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one ...
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Figure 4-2. 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...
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The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instruction ld.d st.d 4.3.6 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if ...
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Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...
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Figure 4-5. Bit 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in page 27. Table 4-2. Priority N/A N/A Mode ...
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All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described ...
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Table 4-3. Reg # 33- ...
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Table 4-3. Reg # 100 101 102 103-191 192-255 4.5 Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have ...
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The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter ...
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Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated ...
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Table 4-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x8000_0000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...
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... Memories 5.1 Embedded Memories • Internal High-Speed Flash – 256KBytes (AT32UC3A3256/S) – 128Kbytes (AT32UC3A3128/S) – 64Kbytes (AT32UC3A364/S) • Internal High-Speed SRAM – 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the High Speed Bud (HSB) matrix – 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix 5 ...
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... Bus Monitor module - BUSMON MCI Mulitmedia Card Interface - MCI MSI Memory Stick Interface - MSI PDCA Peripheral DMA Controller - PDCA INTC Interrupt controller - INTC Size Size AT32UC3A3128S AT32UC3A364S AT32UC3A3128 AT32UC3A364 AT32UC3A4128S AT32UC3A464S AT32UC3A4128 AT32UC3A464 32KByte 32KByte 32KByte 32KByte 64KByte 64KByte 64KByte 64KByte ...
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Table 5-2. Peripheral Address Mapping 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 32072G–11/2011 PM Power Manager - PM RTC Real Time Counter - RTC WDT Watchdog Timer - WDT ...
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Table 5-2. Peripheral Address Mapping 0xFFFF5000 0xFFFF5400 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore ...
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Table 5-3. Port 2 3 32072G–11/2011 Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Local Bus ...
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Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after power controlled by the Power Manager. For specific details, refer to (PM)” on page 6.1 Starting of Clocks After power-up, the device will ...
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Electrical Characteristics 7.1 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -60°C to +150°C Voltage on Input Pin with respect to Ground ........................................-0.3V to 3.6V Maximum Operating Voltage (VDDCORE) ..................... 1.95V Maximum Operating Voltage (VDDIO).............................. 3.6V ...
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DC Characteristics The following characteristics are applicable to the operating temperature range: T specified and are certified for a junction temperature up toT Table 7-1. DC Characteristics Symbol Parameter V DC Supply Peripheral I/Os VDDIO V DC Analog Supply ...
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I/O Pin Output Level Typical Characteristics Figure 7-1. Figure 7-2. 7.3 I/O pin Characteristics These parameters are given in the following conditions: • V DDCORE • V DDIO • Ambient Temperature = 25°C 32072G–11/2011 I/O Pin drive x2 Output ...
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Table 7-2. Normal I/O Pin Characteristics Symbol Parameter f Output frequency MAX t Rise time RISE t Fall time FALL 7.4 Regulator characteristics Table 7-3. Electrical Characteristics Symbol Parameter V Supply voltage (input) VDDIN V Supply voltage (output) VDDCORE I ...
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Analog characteristics 7.5.1 ADC Table 7-5. Electrical Characteristics Symbol Parameter V Analog Power Supply VDDANA Table 7-6. Decoupling Requirements Symbol Parameter C Power Supply Capacitor VDDANA 7.5.2 BOD Table 7-7. 1.8V BOD Level Values Symbol Parameter Value 00 1111b ...
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Table 7-9. BOD Timing Symbol Parameter Minimum time with VDDCORE < T BOD VBOD to detect power failure 7.5.3 Reset Sequence Table 7-10. Electrical Characteristics Symbol Parameter VDDIN/VDDIO rise rate to ensure V DDRR power-on-reset Rising threshold voltage: voltage up ...
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Figure 7-3. VDDIN VDDIO RESET_N Internal BOD33 Reset Internal MCU Reset Figure 7-4. RESET_N Internal BOD33 Reset Internal MCU Reset Figure 7-5. VDDIN VDDIO RESET_N BOD Reset WDT Reset Internal MCU Reset 32072G–11/2011 MCU Cold Start-Up V BOD33LEVEL V RESTART ...
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RESET_N Characteristics Table 7-11. RESET_N Waveform Parameters Symbol Parameter t RESET_N minimum pulse width RESET 32072G–11/2011 Conditions Min. Typ. Max. Unit ...
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Power Consumption The values in tion with operating conditions as follows: •V DDIO •T = 25°C A •I/Os are configured in input, pull-up enabled. Figure 7-6. These figures represent the power consumption measured on the power supplies 32072G–11/2011 Table ...
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Power Consumtion for Different Sleep Modes Table 7-12. Power Consumption for Different Sleep Modes (1) Mode Conditions - CPU running a recursive Fibonacci Algorithm from flash and clocked from PLL0 at f MHz. - Voltage regulator is on. Active ...
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Table 7-13. Peripheral ADC AES ABDAC DMACA EBI EIC GPIO INTC MCI MSI PDCA SDRAM SMC SPI SSC RTC TC TWIM TWIS USART USBB WDT 32072G–11/2011 Typical Cuurent Consumption by Peripheral Typ. Unit 0.5 37 ...
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System Clock Characteristics These parameters are given in the following conditions: • V DDCORE • Ambient Temperature = 25°C 7.7.1 CPU/HSB Clock Characteristics Table 7-14. Core Clock Waveform Parameters Symbol Parameter 1/(t ) CPU Clock Frequency CPCPU t CPU ...
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Oscillator Characteristics The following characteristics are applicable to the operating temperature range: T power supply, unless otherwise specified. 7.8.1 Slow Clock RC Oscillator Table 7-17. RC Oscillator Frequency Symbol Parameter F RC Oscillator Frequency RC 7.8.2 32 KHz Oscillator ...
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Main Oscillators Table 7-19. Main Oscillators Characteristics Symbol Parameter 1/(t ) Oscillator Frequency CPMAIN Internal Load Capacitance ( ESR Crystal Equivalent Series Resistance Duty Cycle t Startup Time ST t XIN Clock High Half-period ...
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ADC Characteristics Table 7-21. Channel Conversion Time and ADC Clock Parameter ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Throughput Rate 1. Corresponds to 13 clock cycles: 3 clock cycles for track and hold acquisition ...
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Table 7-25. Transfer Characteristics in 10-bit mode Parameter Resolution Absolute Accuracy Integral Non-linearity Differential Non-linearity Offset Error Gain Error 7.10 USB Transceiver Characteristics 7.10.1 Electrical Characteristics Table 7-26. Electrical Parameters Symbol Parameter Recommended External USB Series R EXT Resistor R ...
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Table 7-28. Dynamic Power Consumption Symbol Parameter HS Transceiver current consumption HS Transceiver current consumption FS/HS Transceiver current consumption I VDDUTMI FS/HS Transceiver current consumption FS/HS Transceiver current consumption 1. Including 1 mA due to Pull-up/Pull-down current consumption. 34.5.5 USB ...
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EBI Timings 7.11.1 SMC Signals These timings are given for worst case process 85⋅C, VDDIO = 3V and 40 pF load capacitance. Table 7-29. SMC Clock Signal Symbol Parameter 1/(t ) SMC Controller Clock Frequency CPSMC Note: ...
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Table 7-31. SMC Read Signals with no Hold Settings Symbol Parameter SMC Data Setup before NRD High 19 SMC Data Hold after NRD High 20 SMC Data Setup before NCS High 21 SMC Data Hold after NCS High 22 Table ...
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Table 7-33. SMC Write Signals with No Hold Settings (NWE Controlled only) Symbol Parameter SMC Data Out Valid before NWE Rising 43 SMC Data Out Valid after NWE Rising 44 SMC NWE Pulse Width 45 Figure 7-7. SMC Signals for ...
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Figure 7-8. SMC Signals for NRD and NRW Controlled Accesses. A2-A25 A0/A1/NBS[3:0] NCS SMC9 NRD SMC19 D0 - D15 NWE 7.11.2 SDRAM Signals These timings are given for 10 pF load on SDCK and other signals. Table ...
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Table 7-35. SDRAM Clock Signal Symbol Parameter SDRAMC Bank Change before SDCK Rising Edge 13 SDRAMC Bank Change after SDCK Rising Edge 14 SDRAMC CAS Low before SDCK Rising Edge 15 SDRAMC CAS High after SDCK Rising Edge 16 SDRAMC ...
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Figure 7-9. SDRAMC Signals relative to SDCK. SDCK SDRAMC SDRAMC SDRAMC 1 2 SDCKE SDCS RAS CAS SDWE SDA10 A0 - A9, A11 - A13 BA0/BA1 DQM0 - DQM3 D0 - D15 Read D0 - D15 to Write 32072G–11/2011 SDRAMC ...
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JTAG Characteristics 7.12.1 JTAG Interface Signals Table 7-36. JTAG Interface Timing Specification Symbol Parameter JTAG TCK Low Half-period 0 JTAG TCK High Half-period 1 JTAG TCK Period 2 JTAG TDI, TMS Setup before TCK High 3 JTAG TDI, TMS ...
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Figure 7-10. JTAG Interface Signals TCK TMS/TDI TDO Device Inputs Device Outputs 7.13 SPI Characteristics Figure 7-11. SPI Master mode with (CPOL= NCPHA (CPOL= NCPHA= 1) SPCK MISO MOSI 32072G–11/2011 JTAG 2 JTAG 0 JTAG JTAG 3 JTAG ...
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Figure 7-12. SPI Master mode with (CPOL= 0 and NCPHA (CPOL= 1 and NCPHA= 0) SPCK MISO MOSI Figure 7-13. SPI Slave mode with (CPOL= 0 and NCPHA (CPOL= 1 and NCPHA= 0) SPCK MISO MOSI ...
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Table 7-37. SPI Timings Symbol Parameter MISO Setup time before SPCK rises SPI 0 (master) MISO Hold time after SPCK rises SPI 1 (master) SPCK rising to MOSI Delay SPI 2 (master) MISO Setup time before SPCK falls SPI 3 ...
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Flash Memory Characteristics The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory. Flash operating frequency ...
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Mechanical Characteristics 8.1 Thermal Considerations 8.1.1 Thermal Data Table 8-1 Table 8-1. Symbol θ JA θ JC θ JA θ JC θ JA θ JC 8.1.2 Junction Temperature The average chip-junction temperature where: • ...
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Package Drawings Figure 8-1. 32072G–11/2011 TFBGA 144 package drawing 69 ...
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Figure 8-2. LQFP-144 package drawing Table 8-2. Device and Package Maximum Weight 1300 Table 8-3. Package Characteristics Moisture Sensitivity Level Table 8-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32072G–11/2011 mg MSL3 MS-026 E3 70 ...
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Figure 8-3. VFBGA-100 package drawing 32072G–11/2011 71 ...
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Soldering Profile Table 8-5 Table 8-5. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Time Maintained Above 217°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature ...
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... Ordering Information Device Ordering Code AT32UC3A3256S AT32UC3A3256S-ALUT AT32UC3A3256S-ALUR AT32UC3A3256S-CTUT AT32UC3A3256S-CTUR AT32UC3A3256 AT32UC3A3256-ALUT AT32UC3A3256-ALUR AT32UC3A3256-CTUT AT32UC3A3256-CTUR AT32UC3A3128S AT32UC3A3128S-ALUT AT32UC3A3128S-ALUR AT32UC3A3128S-CTUT AT32UC3A3128S-CTUR AT32UC3A3128 AT32UC3A3128-ALUT AT32UC3A3128-ALUR AT32UC3A3128-CTUT AT32UC3A3128-CTUR AT32UC3A364S AT32UC3A364S-ALUT AT32UC3A364S-ALUR AT32UC3A364S-CTUT AT32UC3A364S-CTUR AT32UC3A364 AT32UC3A364-ALUT AT32UC3A364-ALUR AT32UC3A364-CTUT AT32UC3A364-CTUR AT32UC3A4256S AT32UC3A4256S-C1UT AT32UC3A4256S-C1UR AT32UC3A4256 AT32UC3A4256-C1UT AT32UC3A4256-C1UR ...
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Errata 10.1 Rev. H 10.1.1 General DMACA CTLx.DST_TR_WIDTH Fix/Workaround For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH. 10.1.2 Processor and Architecture LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC ...
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ADC Sleep Mode activation needs additional conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep ...
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Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. ...
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TWIM TWIM SR.IDLE goes high immediately when NAK is received When a NAK is received and there is a non-zero number of bytes to be transmitted, SR.IDLE goes high immediately and does not wait for the STOP condition to ...
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FLASHC Corrupted read in flash may happen after fuses write or erase operations (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands) After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands), ...
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Fix/Workaround None. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. When the main clock is RCSYS, TIMER_CLOCK5 is equal to ...
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PDCA transfer. Writing the LINID in the LINIR register will start the transfer whenever the PDCA transfer is ready. The LINID interrupt is only available for the header reception and not available for ...
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Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. ...
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TWIM TWIM SR.IDLE goes high immediately when NAK is received When a NAK is received and there is a non-zero number of bytes to be transmitted, SR.IDLE goes high immediately and does not wait for the STOP condition to ...
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Fix/Workaround The card busy line should be polled through the GPIO pin for commands CMD7, CMD28, CMD29, CMD38, CMD42 and CMD56. The GPIO alternate configuration should be restored after. SSC Frame Synchro and Frame Synchro Data are delayed by one ...
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LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens ...
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Fix/Workaround Make a DTLB Protection (Write) exception handler which permits the interrupt request to be handled in privileged mode. 10.3.2 USB UPCFGn.INTFRQ is irrelevant for isochronous pipe As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full ...
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USART. Configure the Peripheral DMA Controller to signal an interrupt when the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the USART Control Register (CR). This will drive ...
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PDCA PCONTROL.CHxRES is non-functional PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be reset by software. Fix/Workaround Software needs to keep history of performance counters. Transfer error will stall a transmit peripheral handshake interface If a transfer ...
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Fix/Workaround None. 10.3.8 MCI The busy signal of the responses R1b is not taken in account (excepting for CMD12 STOP_TRANSFER not possible to know the busy status of the card during the response (R1b) for the com- mands ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. G– 11/11 1. 11.2 Rev. F – ...
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Description ............................................................................................... 3 2 Overview ................................................................................................... 4 3 Package and Pinout ................................................................................. 6 4 Processor and Architecture .................................................................. 21 5 Memories ................................................................................................ 34 6 Boot Sequence ....................................................................................... 39 7 Electrical Characteristics ...................................................................... 40 32072G–11/2011 2.1 Block Diagram ...................................................................................................4 2.2 ...
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Mechanical Characteristics ................................................................... 68 9 Ordering Information ............................................................................. 73 10 Errata ....................................................................................................... 74 11 Datasheet Revision History .................................................................. 89 32072G–11/2011 7.10 USB Transceiver Characteristics .....................................................................55 7.11 EBI Timings .....................................................................................................57 7.12 JTAG Characteristics .......................................................................................63 7.13 SPI Characteristics ..........................................................................................64 7.14 MCI ...