AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 373

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10. Revision History
10.1
10.2
10.3
10.4
32000D–04/2011
Rev. 32000A-02/2006
Rev. 32000B-11/2007
Rev. 32000C-08/2009
Rev. 32000D-04/2011
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3.
4.
5.
6.
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Initial version.
Improved description of RETE in Instruction Set Chapter.
Corrected description of STC.D in Instruction Set Chapter.
Added micro-TLB miss performance counting.
Added clear-on-compare functionality to COUNT system register
Updated MPU description to match implementation
Added new architecture revision 2 instructions
Corrected typos in the MOVH instruction description.
Corrected Reset address typo in chapter 7.3.1.1
Corrected typos in RETE, DIVS and DIVU detailed instruction set descriptions.
Described new architecture revision 3 secure execution state.
Automatic clear of COUNT on COMPARE match can now be overridden, usually
by writing a bit in the implementation’s CPUCR register.
FlashVault™ description added
Instruction syntax: Each Ri<part> has been replaced by Ri:<part> in the instruc-
tion set summary and descriptions
Added description of bit 7 in Op8 in sleep instruction
Parantheses added to shift instruction descriptions to clarify the order of the
operations
Added cond4 to ld.sb, ld.ub, ld.sh, ld.uh, ld.w, st.b, st.h, st.w instruction descrip-
tion syntax
SE replaced by ZE in st.w{cond4} in the Instruction Set Summary table
AVR32
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