SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 159
SAM9260
Manufacturer Part Number
SAM9260
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9260.pdf
(802 pages)
5.SAM9260.pdf
(47 pages)
Specifications of SAM9260
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
210 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9260 PDF datasheet #4
- SAM9260 PDF datasheet #5
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- Download datasheet (5Mb)
7.9
ARM DDI 0165B
Monitor mode debug
ARM9E-S contains logic that allows the debugging of a system without stopping the
core entirely. This allows the continued servicing of critical interrupt routines while the
core is being interrogated by the debugger. Setting bit 4 of the debug control register
enables the monitor mode debug features of ARM9E-S. When this bit is set, the
EmbeddedICE-RT logic is configured so that a breakpoint or watchpoint causes the
ARM to enter abort mode, taking the Prefetch or Data Abort vectors respectively. There
are a number of restrictions you must be aware of when the ARM is configured for
monitor mode debugging:
•
•
•
•
•
The fact that an abort has been generated by the monitor mode is recorded in the
monitor mode debug status register in coprocessor 14 (see Comms channel monitor
mode debug status register on page 7-18).
Because the monitor mode debug bit does not put the ARM9E-S into debug state, it now
becomes necessary to change the contents of the watchpoint registers while external
memory accesses are taking place, rather than being changed when in debug state. In
the event that the watchpoint registers are written to during an access, all matches from
the affected watchpoint unit using the register being updated are disabled for the cycle
of the update.
Breakpoints and watchpoints cannot be data-dependent. No support is provided
for use of the range functionality. Breakpoints and watchpoints can only be based
on:
—
—
—
—
—
—
The single-step hardware must not be enabled.
External breakpoints or watchpoints are not supported.
The vector catching hardware can be used but must not be configured to catch the
Prefetch or Data Abort exceptions.
No support is provided to mix halt mode debug and monitor mode debug
functionality.
Copyright © 2000 ARM Limited. All rights reserved.
instruction or data addresses
external watchpoint conditioner (DBGEXTERN)
User or Privileged mode access (DnTRANS/InTRANS)
read/write access (watchpoints)
access size (breakpoints ITBIT, watchpoints DMAS[1:0])
chained comparisons.
Debug Interface and EmbeddedICE-RT
7-21
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