SAM9260 Atmel Corporation, SAM9260 Datasheet - Page 95
SAM9260
Manufacturer Part Number
SAM9260
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.SAM9260.pdf
(290 pages)
4.SAM9260.pdf
(802 pages)
5.SAM9260.pdf
(47 pages)
Specifications of SAM9260
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
210 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- M40800 PDF datasheet #2
- SAM9260 PDF datasheet #3
- SAM9260 PDF datasheet #4
- SAM9260 PDF datasheet #5
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- Download datasheet (5Mb)
ARM DDI 0165B
This DABORT to DnMREQ, DSEQ, and DMORE path has been removed from the
ARM9E-S design because:
•
•
Due to this modification, the memory system connected to ARM9E-S is responsible for
ignoring a data memory request made during the cycle of an aborted data transfer. This
is necessary to prevent a following memory access from corrupting memory after an
aborted access. The memory system must ignore DnMREQ, DSEQ, and DMORE in
this case.
a combinational input to output path is undesirable in an ASIC design flow
the path is critical in ARM9TDMI.
Copyright © 2000 ARM Limited. All rights reserved.
CLK
DnRW
DnMREQ
DSEQ
DMORE
DABORT
Address class
signals
WDATA[31:0]
(Write)
Figure 4-5 ARM9TDMI effect of DABORT on following memory access
Write address
Write cycle
(aborted)
Read address
Write data
I cycle
Memory Interface
4-19
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