AD7991 Analog Devices, AD7991 Datasheet
AD7991
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AD7991 Summary of contents
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... I C interface modes. The AD7999 comes in one version. The AD7991/AD7995/AD7999 normally remain in a shutdown state, powering up only for conversions. The conversion process is controlled by a command mode, during which each I operation initiates a conversion and returns the result over the ...
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... Internal Register Structure ............................................................ 20 Configuration Register .............................................................. 20 Sample Delay and Bit Trial Delay............................................. 21 Conversion Result Register ....................................................... 21 Serial Interface ................................................................................ 22 Serial Bus Address...................................................................... 22 Writing to the AD7991/AD7995/AD7999.................................. 23 Reading from the AD7991/AD7995/AD7999............................ 24 Placing the AD7991/AD7995/AD7999 into High Speed Mode................................................................................. 25 Mode of Operation......................................................................... 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27 Rev Page ...
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... V REF ± 1 ± Rev Page AD7991/AD7995/AD7999 = 3.4 MHz, DD REF SCL Unit Test Conditions/Comments See the Sample Delay and Bit Trial Delay section kHz sine wave for f IN from 1.7 MHz to 3.4 MHz kHz sine wave for f ...
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... For 400 kHz, clock stretching is not implemented. Above f SCL 4 See the Terminology section. 5 For f ≤ 1.7 MHz, clock stretching is not implemented; for f SCL 6 Guaranteed by initial characterization. 7 See the Reading from the AD7991/AD7995/AD7999 section. Y Version Min Typ Max ...
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... V 1 ±1 ± Rev Page AD7991/AD7995/AD7999 = 3.4 MHz, DD REF SCL Unit Test Conditions/Comments Sample Delay and Bit Trial Delay See the section kHz sine wave for f IN 1.7 MHz to 3.4 MHz kHz sine wave for f ...
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... For 400 kHz, clock stretching is not implemented. Above f SCL 5 See the Terminology section. 6 For f ≤ 1.7 MHz, clock stretching is not implemented; for f SCL 7 Guaranteed by initial characterization. 8 See the Reading from the AD7991/AD7995/AD7999 section Version Max Min Typ Max 0 0 ...
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... V 1 ±1 ± Rev Page AD7991/AD7995/AD7999 = REF SCL Unit Test Conditions/Comments Sample Delay and Bit Trial Delay See the kHz sine wave for f from 1.7 MHz to 3.4 MHz IN SCL kHz sine wave for f ...
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... For 400 kHz, clock stretching is not implemented. Above f SCL 5 See the Terminology section. 6 For f ≤ 1.7 MHz, clock stretching is not implemented; for f SCL 7 Guaranteed by initial characterization. 8 See the Reading from the AD7991/AD7995/AD7999 section Version Max Min Typ Max 0 0 ...
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... C 300 160 ns Rev Page AD7991/AD7995/AD7999 refers to the capacitive load on the bus line 2 5.5 V and MIN Description Serial clock frequency t , SCL high time HIGH t , SCL low time LOW t , data setup time SU ...
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... AD7991/AD7995/AD7999 Parameter Conditions t Standard mode 10 Fast mode High speed mode C = 100 pF maximum 400 pF maximum B t Standard mode 11 Fast mode High speed mode C = 100 pF maximum 400 pF maximum B t Standard mode 11A Fast mode High speed mode C = 100 pF maximum 400 pF maximum ...
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... Exposure to absolute −0 maximum rating conditions for extended periods may affect −0 0 device reliability. 1 ±10 mA ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 170°C/W 90°C/W 260 + 0° Rev Page AD7991/AD7995/AD7999 ...
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... Analog Input 4. Single-ended analog input channel. The input range IN3 REF external V signal. REF 7 GND Analog Ground. Ground reference point for all circuitry on the AD7991/AD7995/AD7999. All analog input signals should be referred to this AGND voltage Power Supply Input. The Table 8. I ...
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... REF f = 1.7MHz SCL 3000 3500 4000 = 1.7 MHz SCL 1.7 MHz SCL Rev Page AD7991/AD7995/AD7999 1.0 0.8 0.6 POSITIVE INL 0.4 0.2 0 –0.2 NEGATIVE INL –0.4 –0.6 –0.8 –1.0 1.2 1.7 2.2 2.7 3.2 3.7 REFERENCE VOLTAGE (V) Figure 7. INL Error vs. Reference Voltage , f SCL Without Clock Stretching 1.0 0.8 ...
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... MHz Figure 13. THD vs. Input Frequency, V SCL 96 95 +125°C +85°C +25°C 94 –40° 1.7 MHz Figure 14. AD7991 Channel-to-Channel Isolation , f SCL +125°C +85°C –20 +25°C –40°C –40 –60 –80 –100 –120 3.4 MHz SCL Rev Page ...
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... FREQUENCY (kHz) Figure 16. Dynamic Performance 1.71 MHz SCL Without Clock Stretching Full-Scale Input, DD Seven-Term Blackman-Harris Window 3 = 1.71MHz = 10.13kHz Rev Page AD7991/AD7995/AD7999 500 1000 1500 SCL FREQUENCY (kHz) Figure 17. Power vs. SCL Frequency 2.5 V REF ...
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... The AD7991/AD7995/AD7999 are tested using the CCIF standard, where two input frequencies near the maximum input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies ...
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... The AD7991/AD7995/AD7999 are low power, 12-/10-/8-bit, single-supply, 4-channel ADCs. Each part can be operated from a single 2. 5.5 V supply. The AD7991/AD7995/AD7999 provide the user with a 4-channel multiplexer, an on-chip track-and-hold, an ADC, and an I compatible serial interface, all housed in an 8-lead SOT-23 package that offers the user considerable space-saving advantages over alternative solutions ...
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... IN3 REF ANALOG INPUT Figure 21 shows an equivalent circuit of the AD7991/AD7995/ AD7999 analog input structure. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 300 mV. If the signal does exceed this level, the diodes become forward-biased and start conducting current into the substrate ...
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... The maximum source impedance depends on the amount of THD that can be tolerated. THD increases as the source impedance increases and performance degrades. Figure 23 shows the THD vs. the analog input signal frequency for different source impedances at a supply voltage AD7991/AD7995/AD7999 0 –10 –20 –30 –40 – ...
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... INTERNAL REGISTER STRUCTURE CONFIGURATION REGISTER The configuration register is an 8-bit write-only register that is used to set the operating modes of the AD7991/AD7995/AD7999. The bit functions are outlined in Table 10. A single-byte write is necessary when writing to the configuration register the MSB. When the master writes to the AD7991/AD7995/AD7999, the first byte is written to the configuration register. ...
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... ADC in straight binary format. A 2-byte read is necessary to read data from this register. Table 12 shows the contents of the first byte to be read from AD7991/AD7995/AD7999, and Table 13 shows the contents of the second byte to be read bus. This results in ...
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... The devices are available in two versions, the AD7991-0/AD7995-0 and the AD7991-1/AD7995-1/AD7999-1. Each version has a different address (see Table 8), which allows up to two AD7991/AD7995 devices to be connected to a single serial bus. AD7999 has only one version. The serial bus protocol operates as follows: 1 ...
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... SDA START BY MASTER SERIAL BUS ADDRESS BYTE Figure 24. Writing to the AD7991/AD7995/AD7999 Configuration Register The configuration register is an 8-bit register; therefore, only one byte of data can be written to this register. However, writing a single byte of data to this register consists of writing the serial bus write address, followed by the data byte written (see Figure 24). ...
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... MASTER FRAME 1 SERIAL BUS ADDRESS BYTE Figure 25. Reading Two Bytes of Data from the AD7991Conversion Result Register read operation and should not affect the read operation. The master reads back two bytes of data. On the ninth SCLK rising edge of the second byte, if the master sends an ACK, it keeps reading conversion results and the AD7991/AD7995/AD7999 powers up and performs a second conversion ...
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... MASTER FRAME 1 SERIAL BUS ADDRESS BYTE Figure 27. Reading Two Bytes of Data from the Conversion Result Register in High Speed Mode for AD7991 All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is issued, the devices return to fast mode. ...
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... SDA Sr 7-BIT ADDRESS second byte of the conversion result. For the AD7991, this second byte contains the lower eight bits of conversion data. For the AD7995, this second byte contains six bits of conversion data plus two trailing 0s. For the AD7999, this second byte contains four bits of conversion data and four trailing 0s ...
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... AD7995YRJZ-0RL −40°C to +125°C AD7995YRJZ-0500RL7 −40°C to +125°C AD7995ARJZ-0RL −40°C to +125°C AD7999YRJZ-1RL −40°C to +125°C AD7999YRJZ-1500RL7 −40°C to +125°C AD7999ARJZ-1RL −40°C to +125°C EVAL-AD7991EBZ EVAL-AD7995EBZ RoHS Compliant Part. 3.00 2.90 2. 3.00 2.80 2 ...
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... AD7991/AD7995/AD7999 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06461-0-10/10(B) Rev Page ...