STM32F407ZG STMicroelectronics, STM32F407ZG Datasheet - Page 111

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STM32F407ZG

Manufacturer Part Number
STM32F407ZG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F407ZG

Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Rtc
subsecond accuracy, hardware calendar

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STM32F405xx, STM32F407xx
Table 53.
1. TBD stands for “to be defined”.
2. Based on design simulation and/or characterization results, not tested in production.
3. Depends on f
f
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
r(CK)
f(CK)
v(WS)
h(WS)
su(WS)
h(WS)
w(CKH)
w(CKL)
su(SD_MR)
su(SD_SR)
h(SD_MR)
h(SD_SR)
h(SD_MR)
h(SD_SR)
v(SD_ST)
h(SD_ST)
v(SD_MT)
h(SD_MT)
c(CK)
Symbol
(2)
(2)
(2)
(2)
(2)
(2)
(2)(3)
(2)(3)
(2)
(2)(3)
(2)
(2)(3)
(2)
(2)
(2)
(2)
I
2
PCLK
S characteristics
I
I
WS valid time
WS hold time
WS setup time
WS hold time
CK high and low time
Data input setup time
Data input hold time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
2
2
S clock frequency
S clock rise and fall time
. For example, if f
Parameter
Doc ID 022152 Rev 2
PCLK
(1)
=8 MHz, then T
Master
Slave
capacitive load
C
Master
Master
Slave
Slave
Master f
presc = TBD
Master receiver
Slave receiver
Master receiver
Slave receiver
Master f
Slave f
Slave transmitter
(after enable edge)
f
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
f
Master transmitter
(after enable edge)
PCLK
PCLK
L
= 50 pF
Conditions
= TBD
= TBD
PCLK
PCLK
PCLK
PCLK
= 1/f
= TBD
= TBD,
= TBD
PLCLK
=125 ns.
Electrical characteristics
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0
-
-
-
-
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-
-
-
-
-
-
-
-
-
-
111/167
MHz
Unit
ns

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