STM32F407ZG STMicroelectronics, STM32F407ZG Datasheet - Page 126

• Manufacturer Part Number: STM32F407ZG
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
• Manufacturer: STMicroelectronics

Specifications of STM32F407ZG

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Rtc: subsecond accuracy, hardware calendar

Electrical characteristics
Figure 51. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
5.3.25
126/167
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
FSMC characteristics
Asynchronous waveforms and timings
Figure 52
Table 74
with the following FSMC configuration:
●
●
●
●
In all timing tables, the
AddressSetupTime = 1
AddressHoldTime = 0x1
DataSetupTime = 0x1
BusTurnAroundDuration = 0x0
provide the corresponding timings. The results shown in these tables are obtained
through
Buffered/Non-buffered DAC
Figure 55
12-bit
digital to
analog
converter
T
HCLK
represent asynchronous waveforms and
is the HCLK clock period.
Doc ID 022152 Rev 2
Buffer(1)
DACx_OUT
C
R
LOAD
LOAD
STM32F405xx, STM32F407xx
Table 71
ai17157
through