STM32F407ZG STMicroelectronics, STM32F407ZG Datasheet - Page 129

• Manufacturer Part Number: STM32F407ZG
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
• Manufacturer: STMicroelectronics

Specifications of STM32F407ZG

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Rtc: subsecond accuracy, hardware calendar

STM32F405xx, STM32F407xx
Figure 54. Asynchronous multiplexed PSRAM/NOR read waveforms
Table 73.
1. C
2. Based on characterization, not tested in production.
t
t
t
t
t
su(Data_NOE)
t
h(Data_NOE)
t
h(AD_NADV)
t
v(NADV_NE)
t
su(Data_NE)
h(NE_NOE)
t
v(NOE_NE)
h(BL_NOE)
h(Data_NE)
t
Symbol
t
h(A_NOE)
t
v(BL_NE)
t
w(NADV)
v(A_NE)
w(NOE)
t
L
w(NE)
= 30 pF.
FSMC_NBL[1:0]
FSMC_ AD[15:0]
FSMC_A[25:16]
Asynchronous multiplexed PSRAM/NOR read timings
FSMC_NADV
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD(adress) valid hold time after
FSMC_NADV high)
Address hold time after FSMC_NOE high
FSMC_BL time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
Data to FSMC_NEx high setup time
Data to FSMC_NOE high setup time
Data hold time after FSMC_NEx high
Data hold time after FSMC_NOE high
FSMC_NWE
FSMC_NOE
FSMC_NE
Doc ID 022152 Rev 2
Parameter
t
t
t
v(NADV_NE)
v(A_NE)
t
v(A_NE)
t
t
v(NOE_NE)
v(BL_NE)
w(NADV)
Address
Address
t
h(AD_NADV)
t
w(NE)
NBL
t
su(Data_NOE)
t
t
w(NOE)
su(Data_NE)
Data
2T
3T
t
T
T
T
T
T
h(NE_NOE)
HCLK
t
T
HCLK
HCLK
HCLK
HCLK
HCLK
h(BL_NOE)
t
HCLK
h(A_NOE)
Min
HCLK
0
0
0
0
1
-
-
Electrical characteristics
–0.5
– 2
–1
+4
+4
–1
–1
(1)(2)
2T
3T
T
T
t
HCLK
h(Data_NOE)
HCLK
HCLK
t
HCLK
Max
h(Data_NE)
3
2
2
-
-
-
-
-
-
-
-
+0.5
+1
+1
ai14892b
+1
129/167
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns