STM32F407ZG STMicroelectronics, STM32F407ZG Datasheet - Page 134

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STM32F407ZG

Manufacturer Part Number
STM32F407ZG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F407ZG

Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Rtc
subsecond accuracy, hardware calendar

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Electrical characteristics
134/167
Figure 58. Synchronous non-multiplexed NOR/PSRAM read timings
Table 77.
1. C
2. Based on characterization, not tested in production.
t
t
t
t
t
t
t
t
t
t
t
w(CLK)
d(CLKL-NExL)
d(CLKL-NExH)
d(CLKL-NADVL)
d(CLKL-NADVH)
d(CLKL-AV)
d(CLKL-AIV)
d(CLKL-NOEL)
d(CLKL-NOEH)
su(DV-CLKH)
h(CLKH-DV)
Symbol
L
= 30 pF.
Synchronous non-multiplexed NOR/PSRAM read timings
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
FSMC_CLK low to FSMC_NEx high (x= 0…2)
FSMC_CLK low to FSMC_NADV low
FSMC_CLK low to FSMC_NADV high
FSMC_CLK low to FSMC_Ax valid (x=16…25)
FSMC_CLK low to FSMC_Ax invalid (x=16…25)
FSMC_CLK low to FSMC_NOE low
FSMC_CLK low to FSMC_NOE high
FSMC_D[15:0] valid data before FSMC_CLK high
FSMC_D[15:0] valid data after FSMC_CLK high
Doc ID 022152 Rev 2
Parameter
STM32F405xx, STM32F407xx
2T
HCLK
Min
1.5
3
2
6
0
3
-
-
-
-
–0.5
(1)(2)
Max
0.5
0.5
2
0
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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