STM32F407ZG STMicroelectronics, STM32F407ZG Datasheet - Page 71

• Manufacturer Part Number: STM32F407ZG
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
• Manufacturer: STMicroelectronics

Specifications of STM32F407ZG

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Rtc: subsecond accuracy, hardware calendar

STM32F405xx, STM32F407xx
Table 17.
1. Based on characterization, tested in production at V
2. External clock is 4 MHz and PLL is on when f
I
DD
Symbol
Supply current
in Run mode
Typical and maximum current consumption
The MCU is placed under the following conditions:
●
●
●
●
●
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled)
Parameter
At startup, all I/O pins are configured as analog inputs by firmware.
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted to f
30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz, 3 wait states
from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to
168 MHz).
When the peripherals are enabled HCLK is the system clock, f
f
The maximum values are obtained for V
(T
PCLK2
A
), and the typical values for T
= f
External clock
peripherals enabled
External clock
peripherals disabled
HCLK
Conditions
/2, except is explicitly mentioned.
(2)
(3)
HCLK
, all
, all
Doc ID 022152 Rev 2
> 25 MHz.
(3)
DD
max and f
A
= 25 °C and V
168 MHz
144 MHz
120 MHz
168 MHz
144 MHz
120 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz
90 MHz
60 MHz
30 MHz
25 MHz
16 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
2 MHz
f
HCLK
HCLK
DD
max with peripherals enabled.
= 3.6 V and maximum ambient temperature
HCLK
T
DD
A
= 25 °C T
Typ
= 3.3 V unless otherwise specified.
93
76
67
53
37
20
16
11
46
40
37
30
22
12
10
6
4
3
7
4
3
2
frequency (0 wait state from 0 to
A
Electrical characteristics
= 85 °C T
109
89
79
65
49
32
27
23
18
16
15
48
42
33
24
21
19
16
15
14
PCLK1
61
52
Max
= f
(1)
A
HCLK
= 105 °C
117
69
26
23
22
21
96
86
73
56
39
35
30
25
23
22
60
56
50
41
31
29
/4, and
71/167
Unit
mA