STM8S005K6 STMicroelectronics, STM8S005K6 Datasheet

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STM8S005K6

Manufacturer Part Number
STM8S005K6
Description
Value line, 16 MHz STM8S 8-bit MCU, 32 Kbytes Flash, data EEPROM
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8S005K6

Program Memory
32 Kbytes Flash; data retention 20 years at 55 °C after 100 cycles
Data Memory
128 bytes of true data EEPROM; endurance up to 100 k write/erase cycles
Ram
2 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

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Features
Core
Memories
Clock, reset and supply management
January 2012
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
Extended instruction set
Medium-density Flash/EEPROM:
-
-
RAM: 2 Kbytes
2.95 V to 5.5 V operating voltage
Flexible clock control, 4 master clock sources:
-
-
-
-
Clock security system with clock monitor
Power management:
-
-
Program memory: 32 Kbytes of Flash
memory; data retention 20 years at 55°C
after 100 cycles
Data memory: 128 bytes of true data
EEPROM; endurance up to 100 k write/erase
cycles
Low power crystal resonator oscillator
External clock input
Internal, user-trimmable 16 MHz RC
Internal low power 128 kHz RC
Low power modes (wait, active-halt, halt)
Switch-off peripheral clocks individually
Value line, 16 MHz STM8S 8-bit MCU, 32 Kbytes Flash, data
LQFP48 7x7
LQFP32 7x7
EEPROM,10-bit ADC, timers, UART, SPI, I²C
DocID022186 Rev 2
STM8S005K6 STM8S005C6
Interrupt management
Timers
Communications interfaces
Analog-to-digital converter (ADC)
I/Os
Development support
Permanently active, low consumption power-on
and power-down reset
Nested interrupt controller with 32 interrupts
Up to 37 external interrupts on 6 vectors
2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
8-bit basic timer with 8-bit prescaler
Auto wake-up timer
Window and independent watchdog timers
UART with clock output for synchronous
operation, Smartcard, IrDA, LIN
SPI interface up to 8 Mbit/s
I
10-bit, ±1 LSB ADC with up to 10 multiplexed
channels, scan mode and analog watchdog
Up to 38 I/Os on a 48-pin package including 16
high sink outputs
Highly robust I/O design, immune against current
injection
Embedded single wire interface module (SWIM)
for fast on-chip programming and non intrusive
debugging
2
C interface up to 400 Kbit/s
www.st.com
1/103

STM8S005K6 Summary of contents

Page 1

... Power management: - Low power modes (wait, active-halt, halt) - Switch-off peripheral clocks individually January 2012 STM8S005K6 STM8S005C6 EEPROM,10-bit ADC, timers, UART, SPI, I²C • Permanently active, low consumption power-on and power-down reset Interrupt management • Nested interrupt controller with 32 interrupts • ...

Page 2

... Memory map ................................................................................................................25 6.2 Register map ...............................................................................................................26 6.2.1 I/O port hardware register map ............................................................26 6.2.2 General hardware register map ...........................................................29 6.2.3 CPU/SWIM/debug module/interrupt controller registers ......................39 7 Interrupt vector mapping ......................................................................................42 8 Option bytes ...........................................................................................................44 9 Electrical characteristics ......................................................................................49 9.1 Parameter conditions ...................................................................................................49 9.1.1 Minimum and maximum values ...........................................................49 9.1.2 Typical values .......................................................................................49 9.1.3 Typical curves ......................................................................................49 2/103 DocID022186 Rev 2 STM8S005K6 STM8S005C6 ...

Page 3

... STM8S005K6 STM8S005C6 9.1.4 Typical current consumption ................................................................49 9.1.5 Loading capacitor .................................................................................50 9.1.6 Pin input voltage ...................................................................................50 9.2 Absolute maximum ratings ..........................................................................................50 9.3 Operating conditions ...................................................................................................52 9.3.1 VCAP external capacitor ......................................................................54 9.3.2 Supply current characteristics ..............................................................55 9.3.3 External clock sources and timing characteristics ...............................66 9.3.4 Internal clock sources and timing characteristics .................................68 9.3.5 Memory characteristics ........................................................................70 9.3.6 I/O port pin characteristics ...................................................................72 9.3.7 Typical output level curves ...................................................................75 9 ...

Page 4

... Table 45. ADC accuracy with R Table 46. EMS data ................................................................................................................................90 Table 47. EMI data .................................................................................................................................91 4/103 = 5 V ............................................................ 3.3 V ......................................................... ............................................................. 3.3 V ..........................................................61 DD < 10 kΩ .......................................................................87 AIN DDA < 10 kΩ 3.3 V ............................................................88 AIN AIN DDA DocID022186 Rev 2 STM8S005K6 STM8S005C6 = 5 V ............................. 3.3 V .......................... ..................................................59 = 3.3 V ...............................................60 ...

Page 5

... STM8S005K6 STM8S005C6 Table 48. ESD absolute maximum ratings .............................................................................................92 Table 49. Electrical sensitivities .............................................................................................................92 Table 50. 48-pin low profile quad flat package mechanical data ............................................................93 Table 51. 32-pin low profile quad flat package mechanical data .........................................................102 Table 52. Thermal characteristics Table 53. Document revision history ...................................................................................................102 (1) ......................................................................................................97 DocID022186 Rev 2 List of tables ...

Page 6

... V (standard ports) ....................................................................... 3.3 V (standard ports) .................................................................... (high sink ports) ...................................................................... 3.3 V (high sink ports) ................................................................... temperatures ........................................................... temperatures ................................................. temperatures ......................................................80 DD (1) (1) ................................................................................... bus and timing diagram DocID022186 Rev 2 STM8S005K6 STM8S005C6 = 16 MHz ........................................... .................................................. MHz ............................................ ....................................................65 .............................................................83 (1) .......................................................85 ...

Page 7

... STM8S005K6 STM8S005C6 1 Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. • For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016). • For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051). • ...

Page 8

... Table 1: STM8S005xx value line features STM8S005C6 32K 128 2K Advanced control timer (TIM1), General-purpose timers (TIM2 and TIM3), Basic 2 timer (TIM4) SPI UART, Window WDG, Independent WDG, ADC DocID022186 Rev 2 STM8S005K6 STM8S005C6 STM8S005K6 32K 128 2K ...

Page 9

... STM8S005K6 STM8S005C6 3 Block diagram Figure 1: STM8S005xx value line block diagram Reset POR/ PDR Single wire debug interf. Master/slave autosynchro LIN master SPI emul. 400 Kbit/s 8 Mbit channels 1/2/4 kHz beep Reset block Clock controller Reset Detector BOR Clock to peripherals and core ...

Page 10

... Data transfer using the X and Y registers or direct memory-to-memory transfers 4.2 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming. 10/103 DocID022186 Rev 2 STM8S005K6 STM8S005C6 ...

Page 11

... STM8S005K6 STM8S005C6 SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. ...

Page 12

... Data memory area ( 128 bytes) Data EEPROM memory Option bytes UBC area Remains write protected during IAP Program memory area Write access possible for IAP MASTER DocID022186 Rev 2 STM8S005K6 STM8S005C6 Programmable area from 1 Kbyte (2 first pages Kbytes (1 page steps) ) coming from different oscillators ...

Page 13

... STM8S005K6 STM8S005C6 - 16 MHz high-speed internal RC oscillator (HSI) - 128 kHz low-speed internal RC (LSI) • Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ...

Page 14

... LSI clock can be internally connected to TIM3 input capture channel 1 for calibration 4.9 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range kHz. The beeper output port is only available through the alternate function remap option bit AFR7. 14/103 DocID022186 Rev 2 STM8S005K6 STM8S005C6 ...

Page 15

... STM8S005K6 STM8S005C6 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver • 16-bit up, down and up/down autoreload counter with 16-bit prescaler • ...

Page 16

... SPI emulation • High precision baud rate generator • Smartcard emulation • IrDA SIR encoder decoder • LIN master mode • LIN slave mode 16/103 Counting CAPCOM Complem. mode channels outputs DDA DocID022186 Rev 2 STM8S005K6 STM8S005C6 Ext. Timer trigger synchronization/ chaining No ...

Page 17

... STM8S005K6 STM8S005C6 Asynchronous communication (UART mode) • Full duplex communication - NRZ standard format (mark/space) • Programmable transmit and receive baud rates Mbit/s (f following any standard baud rate regardless of the input frequency • Separate enable bits for transmitter and receiver • ...

Page 18

... I²C slave features: - Programmable I2C address detection - Stop bit detection • Generation and detection of 7-bit/10-bit addressing and general call • Supports different communication speeds: - Standard speed (up to 100 kHz) - Fast speed (up to 400 kHz) 18/103 DocID022186 Rev 2 STM8S005K6 STM8S005C6 ...

Page 19

... STM8S005K6 STM8S005C6 5 Pinout and pin description Type Level Output speed Port and control configuration Reset state Table 4: Legend/abbreviations for pinout tables I= Input Output Power supply CM = CMOS Input Output HS = High sink O1 = Slow ( MHz Fast ( MHz Fast/slow programmability with slow as default state after reset ...

Page 20

... OSCOUT/PA2 3 V SSIO_1 VCAP DDIO_1 9 PA4 10 (HS) PA5 11 (HS) 12 (HS) PA6 DocID022186 Rev 2 STM8S005K6 STM8S005C6 36 PG1 35 PG0 34 PC7 /SPI_MISO (HS) 33 PC6 /SPI_MOSI (HS DDIO_2 31 V SSIO_2 30 PC5 /SPI_SCK (HS) 29 PC4 (HS)/TIM1_CH4 28 PC3 (HS)/TIM1_CH3 ...

Page 21

... STM8S005K6 STM8S005C6 1. (HS) high sink capability alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Table 5: Pin description for STM8S005 microcontrollers Pin number Pin name Type LQFP48 LQFP32 1 1 NRST I PA1/ OSC ...

Page 22

... DocID022186 Rev 2 STM8S005K6 STM8S005C6 Main function Default alternate (after reset) function PP 1.8 V regulator capacitor Digital power supply I/O power supply X Port A3 Timer 2 - channel 3 X Port A4 X Port A5 X Port A6 (2) X Port F4 Analog input 12 ...

Page 23

... STM8S005K6 STM8S005C6 Pin number Pin name Type LQFP48 LQFP32 25 17 PE5/SPI_ I/O NSS 26 18 PC1/ I/O TIM1_ CH1/ UART2_CK 27 19 PC2/ I/O TIM1_ CH2 28 20 PC3/ I/O TIM1_ CH3 29 21 PC4/ I/O TIM1_ CH4 30 22 PC5/ SPI_ I/O SCK SSIO_2 DDIO_2 PC6/ SPI_ I/O MOSI ...

Page 24

... DocID022186 Rev 2 STM8S005K6 STM8S005C6 Main function Default alternate (after reset) function PP X Port D1 SWIM data interface X Port D2 Timer 3 - channel 1 X Port D3 Timer 2 - channel 2 X Port D4 Timer 2 - channel 1 X Port D5 UART2 data transmit ...

Page 25

... STM8S005K6 STM8S005C6 6 Memory and register map 6.1 Memory map The following table lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Figure 5: Memory map 0x00 0000 RAM (2 Kbytes)     512 bytes stack ...

Page 26

... Port B input pin value register PB_DDR Port B data direction register PB_CR1 Port B control register 1 PB_CR2 Port B control register 2 PC_ODR Port C data output latch register DocID022186 Rev 2 STM8S005K6 STM8S005C6 End address 0x00 FFFF 0x00 07FF 0x00 407F Reset status 0x00 (1) 0xXX 0x00 ...

Page 27

... STM8S005K6 STM8S005C6 Address Block 0x00 500B 0x00 500C 0x00 500D 0x00 500E 0x00 500F Port D 0x00 5010 0x00 5011 0x00 5012 0x00 5013 0x00 5014 Port E 0x00 5015 0x00 5016 0x00 5017 0x00 5018 0x00 5019 Port F 0x00 501A 0x00 501B ...

Page 28

... Port H control register 2 PI_ODR Port I data output latch register PI_IDR Port I input pin value register PI_DDR Port I data direction register PI_CR1 Port I control register 1 PI_CR2 Port I control register 2 DocID022186 Rev 2 STM8S005K6 STM8S005C6 Reset status 0x00 (1) 0xXX 0x00 0x00 0x00 0x00 (1) 0xXX ...

Page 29

... STM8S005K6 STM8S005C6 6.2.2 General hardware register map Address Block Register label 0x00 5050 to Reserved area (10 bytes) 0x00 5059 0x00 505A Flash 0x00 505B 0x00 505C 0x00 505D 0x00 505E 0x00 505F 0x00 5060 to Reserved area (2 bytes) 0x00 5061 0x00 5062 Flash 0x00 5063 ...

Page 30

... Configurable clock control register CLK_PCKENR2 Peripheral clock gating register 2 CLK_HSITRIMR HSI clock calibration trimming register CLK_SWIMCCR SWIM clock control register WWDG_CR WWDG control register WWDG_WR WWDR window register DocID022186 Rev 2 STM8S005K6 STM8S005C6 Reset status (1) 0xXX 0x01 0x00 0xE1 0xE1 0xXX 0x18 0xFF 0x00 ...

Page 31

... STM8S005K6 STM8S005C6 Address Block Register label 0x00 50D3 to Reserved area (13 bytes) 0x00 50DF 0x00 50E0 IWDG 0x00 50E1 0x00 50E2 0x00 50E3 to Reserved area (13 bytes) 0x00 50EF 0x00 50F0 AWU 0x00 50F1 0x00 50F2 0x00 50F3 BEEP 0x00 50F4 to Reserved area (12 bytes) ...

Page 32

... I C clock control register low 2 I2C_CCRH I C clock control register high 2 I2C_TRISER I C TRISE register 2 I2C_PECR I C packet error checking register DocID022186 Rev 2 STM8S005K6 STM8S005C6 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 ...

Page 33

... STM8S005K6 STM8S005C6 Address Block Register label 0x00 5240 UART2 0x00 5241 0x00 5242 0x00 5243 0x00 5244 0x00 5245 0x00 5246 0x00 5247 0x00 5248 0x00 5249 0x00 524A 0x00 524B 0x00 524C to Reserved area (4 bytes) 0x00 524F 0x00 5250 TIM1 ...

Page 34

... TIM1_PSCRL TIM1 prescaler register low TIM1_ARRH TIM1 auto-reload register high TIM1_ARRL TIM1 auto-reload register low TIM1_RCR TIM1 repetition counter register TIM1_CCR1H TIM1 capture/ compare register 1 high DocID022186 Rev 2 STM8S005K6 STM8S005C6 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ...

Page 35

... STM8S005K6 STM8S005C6 Address Block Register label 0x00 5266 0x00 5267 0x00 5268 0x00 5269 0x00 526A 0x00 526B 0x00 526C 0x00 526D 0x00 526E 0x00 526F 0x00 5270 to Reserved area (147 bytes) 0x00 52FF 0x00 5300 TIM2 0x00 5301 0x00 5302 ...

Page 36

... TIM2_CCR3H TIM2 capture/ compare register 3 high TIM2_CCR3L TIM2 capture/ compare register 3 low TIM3_CR1 TIM3 control register 1 TIM3_IER TIM3 interrupt enable register TIM3_SR1 TIM3 status register 1 DocID022186 Rev 2 STM8S005K6 STM8S005C6 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 ...

Page 37

... STM8S005K6 STM8S005C6 Address Block Register label 0x00 5323 0x00 5324 0x00 5325 0x00 5326 0x00 5327 0x00 5328 0x00 5329 0x00 532A 0x00 532B 0x00 532C 0x00 532D 0x00 532E 0x00 532F 0x00 5330 0x00 5331 to Reserved area (15 bytes) 0x00 533F ...

Page 38

... ADC_TDRH ADC Schmitt trigger disable register high ADC_TDRL ADC Schmitt trigger disable register low ADC_HTRH ADC high threshold register high ADC_HTRL ADC high threshold register low DocID022186 Rev 2 STM8S005K6 STM8S005C6 Reset status 0x00 0x00 0x00 0xFF 0x00 0x00 0x00 0x00 0x00 ...

Page 39

... STM8S005K6 STM8S005C6 Address Block Register label 0x00 540A 0x00 540B 0x00 540C 0x00 540D 0x00 540E 0x00 540F 0x00 5410 to Reserved area (1008 bytes) 0x00 57FF (1) Depends on the previous reset source. (2) Write only register. 6.2.3 CPU/SWIM/debug module/interrupt controller registers Table 9: CPU/SWIM/debug module/interrupt controller registers ...

Page 40

... Interrupt software priority register 4 ITC_SPR5 Interrupt software priority register 5 ITC_SPR6 Interrupt software priority register 6 ITC_SPR7 Interrupt software priority register 7 ITC_SPR8 Interrupt software priority register 8 SWIM_CSR SWIM control status register DocID022186 Rev 2 STM8S005K6 STM8S005C6 Reset status 0x00 0x00 0x00 0x07 0xFF 0x28 0x00 0xFF 0xFF ...

Page 41

... STM8S005K6 STM8S005C6 Address Block 0x00 7F81 to Reserved area (15 bytes) 0x00 7F8F 0x00 7F90 DM 0x00 7F91 0x00 7F92 0x00 7F93 0x00 7F94 0x00 7F95 0x00 7F96 0x00 7F97 0x00 7F98 0x00 7F99 0x00 7F9A 0x00 7F9B to Reserved area (5 bytes) 0x00 7F9F (1) Accessible by debug module only ...

Page 42

... Yes Reserved - End of transfer Yes TIM1 update/ overflow/ - underflow/ trigger/ break TIM1 capture/ compare - TIM update/ overflow - TIM capture/ compare - DocID022186 Rev 2 STM8S005K6 STM8S005C6 Wakeup from Vector active-halt address mode Yes 0x00 8000 - 0x00 8004 - 0x00 8008 Yes 0x00 800C - 0x00 8010 ...

Page 43

... STM8S005K6 STM8S005C6 IRQ Source no. block 15 TIM3 16 TIM3 UART2 21 UART2 22 ADC1 23 TIM 24 Flash Reserved (1) Except PA1 Description Wakeup from halt mode Update/ overflow - Capture/ compare - Reserved - Reserved - interrupt Yes Tx complete - Receive register DATA - FULL ADC1 end of conversion/ - analog watchdog interrupt ...

Page 44

... AFR5 AFR4 AFR3 AFR6 NAFR6 NAFR5 NAFR4 NAFR3 HSI LSI_ EN TRIM NHSI NLSI_ TRIM EN EXT CLK NEXT CLK DocID022186 Rev 2 STM8S005K6 STM8S005C6 Factory default setting 00h 00h FFh AFR2 AFR1 AFR0 00h NAFR2 NAFR1 NAFR0 FFh IWDG WWDG WWDG ...

Page 45

... STM8S005K6 STM8S005C6 Addr. Option Option Option bits name byte no. 7 NOPT6 0x480C Reserved OPT7 0x480D Reserved Reserved NOPT7 0x480E Reserved OPTBL 0x487E Bootloader BL[7:0] NOPTBL 0x487F NBL[7:0] Option byte no. OPT0 OPT1 OPT2 OPT3 Table 12: Option byte description Description ROP[7:0] Memory readout protection (ROP) ...

Page 46

... PRSC[1:0] AWU clock prescaler 0x: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler HSECNT[7:0]:HSE crystal oscillator stabilization time 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles DocID022186 Rev 2 STM8S005K6 STM8S005C6 ...

Page 47

... STM8S005K6 STM8S005C6 Option byte no. OPT6 OPT7 OPTBL Table 13: Description of alternate function remapping bits [7:0] of OPT2 Option byte no. OPT2 Description Reserved Reserved BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector ...

Page 48

... AFR1 Alternate function remapping option 1 0: AFR1 remapping option inactive: Default alternate functions 1: Port A3 alternate function = TIM3_CH1; port D2 alternate function TIM2_CH3. AFR0 Alternate function remapping option 0 0: AFR0 remapping option inactive: Default alternate function 1: Port D3 alternate function = ADC_ETR. DocID022186 Rev 2 STM8S005K6 STM8S005C6 (2) . (2) . (2) . ...

Page 49

... STM8S005K6 STM8S005C6 9 Electrical characteristics 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at T the selected temperature range) ...

Page 50

... Supply voltage (including V DDx SS V Input voltage on true open drain pins (PE1, IN PE2) 50/103 Figure 7: Pin loading conditions 50 pF Figure 8: Pin input voltage V IN Table 14: Voltage characteristics V DDA and (2) DocID022186 Rev 2 STM8S005K6 STM8S005C6 STM8 PIN STM8 PIN Min Max (1) ) -0.3 6.5 DDIO V - 0.3 6.5 SS Unit V ...

Page 51

... STM8S005K6 STM8S005C6 Symbol Ratings Input voltage on any other pin |V - Variations between different power pins DDx Variations between all the different ground pins SSx SS V Electrostatic discharge voltage ESD (1) All power (V DD connected to the external power supply (2) I must never be exceeded. This is implicitly insured if V ...

Page 52

... and ground (V DDIO DDA /V DDIO SSIO maximum must always be respected IN INJ(PIN) Table 16: Thermal characteristics Ratings Storage temperature range Maximum junction temperature DocID022186 Rev 2 STM8S005K6 STM8S005C6 (1) Max. ±4 ±4 (6) ±4 (6) ± pins must always be SS SSIO SSA pins. maximum is respected. ...

Page 53

... STM8S005K6 STM8S005C6 Symbol f CPU DD_IO (1) VCAP ( (1) Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum value must be respected for the full application range. ...

Page 54

... Figure 9: f CPUmax f CPU (MHz Functionality guaranteed @ ° 4.0 2.95 Supply voltage Conditions rise time rate fall time rate V rising DD DocID022186 Rev 2 STM8S005K6 STM8S005C6 versus V DD 5.0 5.5 Min Typ Max (1) 2.0 ∞ (1) 2.0 ∞ 1.7 2.65 2.8 2.95 2.58 2.7 2.88 70 Unit µ ...

Page 55

... STM8S005K6 STM8S005C6 1. ESR is the equivalent series resistance and ESL is the equivalent inductance. 9.3.2 Supply current characteristics The current consumption is measured as described in 9.3.2.1 Total current consumption in run mode Table 19: Total current consumption with code execution in run mode at V Symbol Parameter I Supply DD(RUN) current in run ...

Page 56

... MHz/ LSI RC osc. CPU MASTER = 128 kHz (128 kHz) Conditions MHz HSE crystal osc. CPU MASTER (16 MHz) HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz) DocID022186 Rev 2 STM8S005K6 STM8S005C6 (1) Typ Max Unit 7.7 7.0 8.0 7.0 8.0 1.5 (2) 1.35 2.0 0.75 0 (1) Typ Max Unit 2 ...

Page 57

... STM8S005K6 STM8S005C6 Symbol Parameter Supply current in run mode, code executed from Flash (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. Conditions /128 HSE user ext. clock CPU MASTER = 125 kHz (16 MHz) HSI RC osc. ...

Page 58

... MHz/ 128 LSI RC osc. CPU MASTER kHz (128 kHz) Conditions HSE crystal osc. CPU MASTER MHz (16 MHz) HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz) DocID022186 Rev 2 STM8S005K6 STM8S005C6 = (1) Typ Max Unit 2.15 mA 1.55 2.0 1.5 1.9 1.3 0.7 (2) 0 (1) Typ Max Unit 1 ...

Page 59

... STM8S005K6 STM8S005C6 Symbol Parameter (1) Data based on characterization results, not tested in production. (2) Default clock configuration measured with all peripherals off. 9.3.2.3 Total current consumption in active halt mode Table 23: Total current consumption in active halt mode at V Symbol Parameter I Supply DD(AH) current in active halt mode Conditions ...

Page 60

... Power-down mode Conditions (3) Main Flash mode voltage regulator (2) (MVR) On Operating mode Power-down mode Off Operating mode Power-down mode DocID022186 Rev 2 STM8S005K6 STM8S005C6 Typ Max at 85 (1) °C Clock source LSI RC osc. 68 120 (128 kHz 3 Typ Max at 85 (1) °C Clock source HSE crystal osc ...

Page 61

... STM8S005K6 STM8S005C6 (1) Data based on characterization results, not tested in production. (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. 9.3.2.4 Total current consumption in halt mode Table 25: Total current consumption in halt mode at V Symbol Parameter I Supply current in DD(H) halt mode (1) Data based on characterization results, not tested in production ...

Page 62

... MVR voltage Flash in regulator power-down (4) (5) off mode (5) Flash in operating mode (5) Flash in power-down mode CPU. Conditions 3 DocID022186 Rev 2 STM8S005K6 STM8S005C6 (1) Typ Unit Max HSI (6) (6) (after 1 2 wakeup) HSI (6) (after 3 wakeup) HSI (6) (after 48 wakeup) HSI (6) (after ...

Page 63

... STM8S005K6 STM8S005C6 Symbol Parameter t Reset pin release to RESETBL vector fetch (1) Data guaranteed by design, not tested in production. (2) Characterized with all I/Os tied to V 9.3.2.7 Current consumption of on-chip peripherals Subject to general operating conditions for V HSI internal RC/f Symbol Parameter I TIM1 supply current DD(TIM1) I TIM2 supply current ...

Page 64

... V HSE user external clock, f DD(RUN 2.95 2.9 2.85 2.8 2.75 2.7 2.65 2.6 2.55 2.5 2.5 3 3.5 4 4.5 V [V] DD vs. f HSE user external clock, V DD(RUN) CPU , 5 4.5 4 3.5 3 2.5 2 1 fcpu [MHz] DocID022186 Rev 2 STM8S005K6 STM8S005C6 = 16 MHz CPU -40°C 25°C 85°C 5 5.5 6 IID10235 = -40°C 25°C 85° IID10236 ...

Page 65

... STM8S005K6 STM8S005C6 Figure 13: Typ. I Figure 14: Typ. I Figure 15: Typ. I vs. V HSI RC osc, f DD(RUN 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 2.5 3 3.5 4 4.5 V [V] DD vs. V HSE user external clock, f DD(WFI 2.4 2.2 2 1.8 1.6 1.4 1.2 1 2.5 3 3.5 4 4.5 V [ HSE user external clock V DD(WFI) CPU 3 2.5 2 1 fcpu [MHz] DocID022186 Rev 2 ...

Page 66

... Data based on characterization results, not tested in production. 66/103 vs HSI RC osc, f DD(WFI 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 2.5 3 3 [V] DD and Conditions Min 0 0 < V < DocID022186 Rev 2 STM8S005K6 STM8S005C6 = 16 MHz CPU -40°C 25°C 85°C 5.5 6 IID10240 Max Unit 16 MHz μA ...

Page 67

... STM8S005K6 STM8S005C6 V HSEH V HSEL HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time ...

Page 68

... HSI 68/103 Figure 18: HSE oscillator circuit diagram OSCIN Resonator OSCOUT C L2 equation × R (2Co + Table 32: HSI oscillator characteristics Conditions DocID022186 Rev 2 STM8S005K6 STM8S005C6 f HSE to core Consumption control STM8 and Min Typ Max 16 Unit MHz ...

Page 69

... STM8S005K6 STM8S005C6 Symbol Parameter ACC Accuracy of HSI HSI oscillator Accuracy of HSI oscillator (factory calibrated) t HSI oscillator su(HSI) wakeup time including calibration I HSI oscillator power DD(HSI) consumption (1) Refer to application note. (2) Guaranteed by design, not tested in production. (3) Data based on characterization results, not tested in production. ...

Page 70

... V [V] DD Table 34: RAM and hardware registers Conditions (1) Halt mode (or reset) for the value of V IT-max = -40 to 85°C. A DocID022186 Rev 2 STM8S005K6 STM8S005C6 Min Typ Max 128 ( temperatures DD -40°C 25°C 85°C 5 5.5 6 IID10242 Min Unit (2) V ...

Page 71

... STM8S005K6 STM8S005C6 Table 35: Flash program memory/data EEPROM memory Symbol Parameter V Operating voltage (all modes, DD execution/write/erase) t Standard programming time prog (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) Fast programming time for 1 block (128 bytes) t Erase time for 1 block (128 bytes) erase N Erase/write cycles ...

Page 72

... IN SS Fast I/Os load = 50 pF Standard and high sink I/OsLoad = ≤ V ≤ ≤ V ≤ Injection current ±4 mA (2) DocID022186 Rev 2 STM8S005K6 STM8S005C6 unless otherwise specified. All unused A Min Typ Max -0 700 (3) ...

Page 73

... STM8S005K6 STM8S005C6 Figure 21: Typical V Figure 22: Typical pull-up resistance vs V Figure 23: Typical pull-up current The pull- pure resistor (slope goes through 0). and 2.5 3 3.5 4 4 2.5 3 3 [V] DD 140 120 100 ...

Page 74

... V DD Conditions Table 39: Output driving current (high sink ports) Conditions DocID022186 Rev 2 STM8S005K6 STM8S005C6 Min Max Unit (1) 1.0 V 2.0 (1) 2.0 V 2.4 Max Unit (1) = 3 1 2.0 DD Min ...

Page 75

... STM8S005K6 STM8S005C6 Symbol Parameter Output low level with four pins sunk V Output high level with four pins OH sourced Output high level with eight pins sourced Output high level with four pins sourced (1) Data based on characterization results, not tested in production 9.3.7 Typical output level curves The following figures show typical output level curves measured with output on a single pin ...

Page 76

... (true open drain ports -40°C 2 25°C 1.75 85°C 1.5 1.25 1 0.75 0.5 0. [mA 3.3 V (true open drain ports -40°C 2 25°C 1.75 85°C 1.5 1.25 1 0.75 0.5 0. [mA] OL DocID022186 Rev 2 STM8S005K6 STM8S005C6 IID10225 IID10226 IID10227 ...

Page 77

... STM8S005K6 STM8S005C6 Figure 28: Typ -40°C 1.5 25°C 1.25 85°C 1 0.75 0.5 0. Figure 29: Typ -40°C 1.5 25°C 1.25 85°C 1 0.75 0.5 0. Figure 30: Typ -40°C 2 25°C 1.75 85°C 1.5 1.25 1 0.75 0.5 0. DocID022186 Rev 2 Electrical characteristics = 5 V (high sink ports) ...

Page 78

... (high sink ports -40°C 2 25°C 1.75 85°C 1.5 1.25 1 0.75 0.5 0. [mA 3.3 V (high sink ports -40°C 2 25°C 1.75 85°C 1.5 1.25 1 0.75 0.5 0. [mA] OH DocID022186 Rev 2 STM8S005K6 STM8S005C6 IID10231 20 25 IID10232 12 14 IID10233 ...

Page 79

... STM8S005K6 STM8S005C6 9.3.8 Reset pin characteristics Subject to general operating conditions for V Symbol Parameter V IL(NRST) NRST input low (1) level voltage V IH(NRST) NRST input high level voltage V OL(NRST) NRST output low level voltage R PU(NRST) NRST pull-up (2) resistor t I FP(NRST) NRST input filtered (3) pulse t IN FP(NRST) ...

Page 80

... V [ 2.5 3 3 [V] DD 140 120 100 2.5 3 3.5 4 4.5 V [V] DD DocID022186 Rev 2 STM8S005K6 STM8S005C6 @ 3 temperatures DD -40°C 25°C 85°C 5 5.5 6 IID10248 @ 3 temperatures DD -40°C 25°C 85°C 5.5 6 IID10234 @ 3 temperatures DD -40°C 25°C 85°C 5 5.5 6 IID10246 ...

Page 81

... STM8S005K6 STM8S005C6 The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below V NRST pin characteristics For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current ...

Page 82

... Slave mode Master mode Slave mode Slave mode Slave mode Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) Master mode (after enable edge) DocID022186 Rev 2 STM8S005K6 STM8S005C6 Min Max Unit SCK SCK ...

Page 83

... STM8S005K6 STM8S005C6 Figure 38: SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 t a(SO) MISO OUT P UT MOSI I NPUT Figure 39: SPI timing diagram - slave mode and CPHA = 1 NSS input t SU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t a(SO) MISO OUT P UT MOSI I NPUT 1 ...

Page 84

... High t c(SCK) t w(SCKH) t su(MI) t w(SCKL) MS BIN t h(MI OUT OUT t v(MO) 2 Table 42 characteristics Standard mode I (2) Min 4.7 4.0 250 (3) 0 DocID022186 Rev 2 STM8S005K6 STM8S005C6 (1) t r(SCK) t f(SCK LSB IN LSB OUT t h(MO) and 0 (1) C Fast mode I C (2) (2) (2) Max Min Max 1 ...

Page 85

... STM8S005K6 STM8S005C6 Symbol Parameter t START condition hold time h(STA) t Repeated START condition su(STA) setup time t STOP condition setup time su(STO) t STOP to START condition time w(STO:STA) (bus free) C Capacitive load for each bus line b ( must be at least 8 MHz to achieve max fast I ...

Page 86

... REF+ REF MHz ADC MHz ADC MHz ADC MHz ADC (3 pF max) can be charged/discharged AIN After the end of the sample time t S. DocID022186 Rev 2 STM8S005K6 STM8S005C6 unless otherwise specified. A Min Typ Max Unit 1.0 4.0 MHz 1.0 6.0 3.0 5.5 V (1) 2. DDA (1) 0 ...

Page 87

... STM8S005K6 STM8S005C6 changes of the analog input voltage have no effect on the conversion result. Values for the sample clock t S Symbol Parameter |E | Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error L (1) Data based on characterisation results, not tested in production. ...

Page 88

... MHz ADC ( MHz ADC MHz ADC ( MHz ADC MHz ADC ( MHz ADC MHz ADC does not affect the ADC accuracy. DocID022186 Rev 2 STM8S005K6 STM8S005C6 and ΣI INJ(PIN) INJ(PIN) < 10 kΩ 3.3 V AIN DDA (1) Typ Max 1.1 2.0 1.6 2.5 0.7 1.5 1.3 2.0 0.2 1.5 0.5 2.0 0.7 1 ...

Page 89

... STM8S005K6 STM8S005C6 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line E = Total unadjusted error: maximum deviation between the actual and the ideal transfer T curves Offset error: deviation between the first actual transition and the first ideal one. ...

Page 90

... V DD and V SS pins to induce a functional disturbance 90/103 Table 46: EMS data Conditions °C, f MASTER = 16 MHz, conforming to IEC 1000-4 °C ,f MASTER = 16 MHz,conforming to IEC 1000-4-4 DocID022186 Rev 2 STM8S005K6 STM8S005C6 and Level/ class (1) 2/B (1) 4/A ...

Page 91

... STM8S005K6 STM8S005C6 (1) Data obtained with HSI clock configuration, after applying HW recommendations described in AN2860 (EMC guidelines for STM8S microcontrollers). 9.3.12.3 Electromagnetic interference (EMI) Emission tests conform to the IEC61967-2 standard for test software, board layout and pin loading. Symbol Parameter S Peak level EMI SAE EMI ...

Page 92

... JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). 92/103 Table 48: ESD absolute maximum ratings Conditions T = +25°C, A conforming to JESD22-A114 T =+25°C, conforming A to JESD22-C101 Table 49: Electrical sensitivities Conditions T = +25 ° +85 °C A DocID022186 Rev 2 STM8S005K6 STM8S005C6 Class Maximum Unit (1) value A 2000 V IV 1000 V (1) Class A A ...

Page 93

... STM8S005K6 STM8S005C6 10 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK trademark. 10.1 48-pin LQFP package mechanical data ...

Page 94

... DocID022186 Rev 2 STM8S005K6 STM8S005C6 (1) Typ Max 0.2756 0.2835 0.2165 0.3543 0.3622 0.2756 0.2835 0.2165 0.0197 0.0236 0.0295 0.0394 3.5° 7.0° 0.0031 ...

Page 95

... STM8S005K6 STM8S005C6 10.2 32-pin LQFP package mechanical data Pin 1 1 identification Table 51: 32-pin low profile quad flat package mechanical data Dim. mm Min A A1 0.050 A2 1.350 b 0.300 c 0.090 D 8.800 D1 6.800 D3 E 8.800 E1 6.800 Figure 45: 32-pin low profile quad flat package ( ...

Page 96

... Values in inches are converted from mm and rounded to 4 decimal digits 96/103 inches Typ Max Min 5.600 0.800 0.600 0.750 0.0177 1.000 3.5° 7.0° 0° 0.100 DocID022186 Rev 2 STM8S005K6 STM8S005C6 (1) Typ Max 0.2205 0.0315 0.0236 0.0295 0.0394 3.5° 7.0° 0.0039 ...

Page 97

... STM8S005K6 STM8S005C6 11 Thermal characteristics The maximum chip junction temperature (T Operating conditions The maximum chip-junction temperature, T the following equation Jmax Amax Where: • the maximum ambient temperature in °C Amax • Θ is the package junction-to-ambient thermal resistance in ° C/W JA • the sum of P Dmax • ...

Page 98

... C + (59° C/W x 464 mW) = 75°C + 27°C = 102° C Jmax This is within the range of the suffix 6 version parts (-40 < T must be ordered at least with the temperature range suffix 6. 98/103 = 82.5 mW and P 360 mW: IOmax DocID022186 Rev 2 STM8S005K6 STM8S005C6 = < 106° C). In this case, parts ...

Page 99

... STM8S005K6 STM8S005C6 12 Ordering information Figure 46: STM8S005xx value line ordering information scheme Example: Product class Family type S = Standard Sub-family type 005 = Value line STM8S005x Pin count pins pins Program memory size Kbytes Package type T = LQFP Temperature range 6 = -40 ° °C Package pitch No character = 0 ...

Page 100

... STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs Kbytes of code. 100/103 DocID022186 Rev 2 STM8S005K6 STM8S005C6 ...

Page 101

... STM8S005K6 STM8S005C6 13.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop – Full-featured integrated development environment from ST, featuring • Seamless integration of C and ASM toolsets • ...

Page 102

... Table 53: Document revision history Changes 1 Initial release. 2 Updated t in Table 35: Flash program memory/data RET EEPROM memory. Updated R in Table 40: NRST pin characteristics PU 36: I/O static characteristics. Updated notes related to V DocID022186 Rev 2 STM8S005K6 STM8S005C6 and Table in Operating conditions. CAP ...

Page 103

... STM8S005K6 STM8S005C6 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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