STM8S005K6 STMicroelectronics, STM8S005K6 Datasheet - Page 11

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STM8S005K6

Manufacturer Part Number
STM8S005K6
Description
Value line, 16 MHz STM8S 8-bit MCU, 32 Kbytes Flash, data EEPROM
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8S005K6

Program Memory
32 Kbytes Flash; data retention 20 years at 55 °C after 100 cycles
Data Memory
128 bytes of true data EEPROM; endurance up to 100 k write/erase cycles
Ram
2 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

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STM8S005K6 STM8S005C6
4.3
4.4
SWIM
Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.
Interrupt controller
Flash program and data EEPROM memory
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(512 bytes) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
R/W to RAM and peripheral registers in real-time
R/W access to all resources by stalling the CPU
Breakpoints on all program-memory instructions (software breakpoints)
Two advanced breakpoints, 23 predefined configurations
Nested interrupts with three software priority levels
32 interrupt vectors with hardware priority
Up to 37 external interrupts on 6 vectors including TLI
Trap and reset interrupts
32 Kbytes of Flash program single voltage Flash memory
128 bytes true data EEPROM
Read while write: Writing in data memory possible while executing code in program memory
User option byte area
Main program memory: 32 Kbytes minus UBC
User-specific boot code (UBC): Configurable up to 32 Kbytes
DocID022186 Rev 2
Product overview
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